公开(公告)号：US07704854B2

公开(公告)日：2010-04-27

申请号：US12115690

申请日：2008-05-06

申请人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

发明人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76283

摘要： The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.

摘要翻译： 本发明涉及一种方法，包括在至少一个SIO层中蚀刻至少一个浅沟槽; 在SIO层和SIO层的界面处形成电介质衬垫; 在电介质衬垫上的浅沟槽中形成金属或金属合金层; 并在金属或金属合金上用氧化物填充浅沟槽。

公开(公告)号：US20090280619A1

公开(公告)日：2009-11-12

申请号：US12115690

申请日：2008-05-06

申请人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

发明人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76283

摘要： The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.

摘要翻译： 本发明涉及一种方法，包括在至少一个SIO层中蚀刻至少一个浅沟槽; 在SIO层和SIO层的界面处形成电介质衬垫; 在电介质衬垫上的浅沟槽中形成金属或金属合金层; 并在金属或金属合金上用氧化物填充浅沟槽。

公开(公告)号：US07855428B2

公开(公告)日：2010-12-21

申请号：US12115699

申请日：2008-05-06

申请人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

发明人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76283

摘要： The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SOI. A dielectric liner is formed at an interface of the SOI within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.

摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于辐射硬总剂量免疫的导电衬垫的设计结构及其结构。 该结构包括至少一个具有氧化物材料并在SOI中形成的浅沟槽隔离结构。 在所述至少一个浅沟槽隔离结构内的SOI的界面处形成电介质衬垫。 在所述至少一个浅沟槽隔离结构中以及所述电介质衬垫和所述氧化物材料之间形成金属或金属合金层。

公开(公告)号：US20090278226A1

公开(公告)日：2009-11-12

申请号：US12115699

申请日：2008-05-06

申请人： Robert H. DENNARD ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

发明人： Robert H. DENNARD ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

IPC分类号： H01L29/06

CPC分类号： H01L21/76283

摘要： The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is formed at an interface of the SIO within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.

摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于辐射硬总剂量免疫的导电衬垫的设计结构及其结构。 该结构包括至少一个具有氧化物材料并形成在SIO中的浅沟槽隔离结构。 电介质衬垫形成在所述至少一个浅沟槽隔离结构内的SIO的界面处。 在所述至少一个浅沟槽隔离结构中以及所述电介质衬垫和所述氧化物材料之间形成金属或金属合金层。

公开(公告)号：US08232179B2

公开(公告)日：2012-07-31

申请号：US12571483

申请日：2009-10-01

申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US08679941B2

公开(公告)日：2014-03-25

申请号：US13422138

申请日：2012-03-16

申请人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E Cummings ,  Lisa F Edge ,  Balasubramanian S. Haran ,  David V Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US20120178236A1

公开(公告)日：2012-07-12

申请号：US13422138

申请日：2012-03-16

申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US20110081765A1

公开(公告)日：2011-04-07

申请号：US12571483

申请日：2009-10-01

申请人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Lisa F. Edge ,  Balasubramanian S. Haran ,  David V. Horak ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

摘要翻译： 提供一种形成半导体器件的方法，其中在一个实施例中，STI填充物在衬垫氮化物和衬垫氧化物层下方凹入到与衬底的顶表面基本上共面的水平。 至少形成凹入的STI填充材料的上表面，形成薄（具有在约10埃-120埃范围内的厚度）耐湿蚀刻层。 薄的耐湿蚀刻层比至少衬垫氧化物层更耐湿蚀刻工艺。 薄的耐湿蚀刻层可以是耐火电介质材料，或诸如HfO x，Al y O x，ZrO x，HfZrO x和HfSiO x的电介质。 本发明的耐湿蚀刻层提高了后续湿蚀刻处理步骤的湿法蚀刻预算。

公开(公告)号：US08790991B2

公开(公告)日：2014-07-29

申请号：US13011546

申请日：2011-01-21

申请人： Jason E. Cummings ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sanjay Mehta

发明人： Jason E. Cummings ,  Balasubramanian S. Haran ,  Hemanth Jagannathan ,  Sanjay Mehta

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L21/76224 ,  H01L21/02107 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

摘要翻译： 提供浅沟槽隔离区域，其中空隙形成基本上或完全从其中消除。 浅沟槽隔离减轻半导体衬底的两个有源区域之间的有源短路。 浅沟槽隔离区域包括存在于形成在半导体衬底中的沟槽的侧壁和底壁上的双层衬垫。 本公开的双层衬垫包括从底部到顶部的浅沟槽隔离衬垫，例如半导体氧化物和/或氮化物，以及高k衬里，例如介电常数大于硅的介电材料 氧化物。

公开(公告)号：US20130264641A1

公开(公告)日：2013-10-10

申请号：US13442168

申请日：2012-04-09

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Sanjay Mehta ,  Stefan Schmitz

IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/76283 ,  H01L27/1203

摘要： A thin BOX ETSOI device with robust isolation and method of manufacturing. The method includes providing a wafer with at least a pad layer overlying a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer, wherein the first semiconductor layer has a thickness of 10 nm or less. The process continues with etching a shallow trench into the wafer, extending partially into the second semiconductor layer and forming first spacers on the sidewalls of said shallow trench. After spacer formation, the process continues by etching an area directly below and between the first spacers, exposing the underside of the first spacers, forming second spacers covering all exposed portions of the first spacers, wherein the pad oxide layer is removed, and forming a gate structure over the first semiconductor wafer.

摘要翻译： 薄型BOX ETSOI器件，具有强大的隔离性和制造方法。 该方法包括提供晶片至少一覆盖在覆盖第二半导体层的氧化物层上的第一半导体层的焊盘层，其中第一半导体层具有10nm或更小的厚度。 该过程继续蚀刻到晶片中的浅沟槽，部分地延伸到第二半导体层中并且在所述浅沟槽的侧壁上形成第一间隔物。 在间隔物形成之后，该过程继续蚀刻直接在第一间隔物下面和之间的区域，暴露第一间隔物的下侧，形成覆盖第一间隔物的所有暴露部分的第二间隔区，其中除去氧化垫层， 第一半导体晶片上的栅极结构。