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    Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer
    2.
    发明授权
    Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer 有权
    在浅沟槽隔离结构和掩埋氧化物层之间的界面处的导电衬垫

    公开(公告)号：US07855428B2

    公开(公告)日：2010-12-21

    申请号：US12115699

    申请日：2008-05-06

    申请人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

    发明人： Robert H. Dennard ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76283

    摘要： The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SOI. A dielectric liner is formed at an interface of the SOI within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.

    摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于辐射硬总剂量免疫的导电衬垫的设计结构及其结构。 该结构包括至少一个具有氧化物材料并在SOI中形成的浅沟槽隔离结构。 在所述至少一个浅沟槽隔离结构内的SOI的界面处形成电介质衬垫。 在所述至少一个浅沟槽隔离结构中以及所述电介质衬垫和所述氧化物材料之间形成金属或金属合金层。

    STRUCTURE FOR CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY AND STRUCTURE THEREOF
    3.
    发明申请
    STRUCTURE FOR CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY AND STRUCTURE THEREOF 有权
    导电衬里结构用于RAD硬总量剂量的免疫和结构

    公开(公告)号：US20090278226A1

    公开(公告)日：2009-11-12

    申请号：US12115699

    申请日：2008-05-06

    申请人： Robert H. DENNARD ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

    发明人： Robert H. DENNARD ,  Mark C. Hakey ,  David V. Horak ,  Sanjay Mehta

    IPC分类号： H01L29/06

    CPC分类号： H01L21/76283

    摘要： The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SIO. A dielectric liner is formed at an interface of the SIO within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.

    摘要翻译： 本发明涉及一种设计结构，更具体地，涉及一种用于辐射硬总剂量免疫的导电衬垫的设计结构及其结构。 该结构包括至少一个具有氧化物材料并形成在SIO中的浅沟槽隔离结构。 电介质衬垫形成在所述至少一个浅沟槽隔离结构内的SIO的界面处。 在所述至少一个浅沟槽隔离结构中以及所述电介质衬垫和所述氧化物材料之间形成金属或金属合金层。

    Implantation of gate regions in semiconductor device fabrication
    8.
    发明授权
    Implantation of gate regions in semiconductor device fabrication 失效
    在半导体器件制造中植入栅极区域

    公开(公告)号：US07557023B2

    公开(公告)日：2009-07-07

    申请号：US11532189

    申请日：2006-09-15

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L21/425

    CPC分类号： H01L29/66545 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659

    摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

    摘要翻译： 半导体制造方法。 该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。 栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。 半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。 接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。 接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。

    Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors
    10.
    发明申请
    Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors 有权
    通过串联电阻同时调节多个存储单元

    公开(公告)号：US20080185652A1

    公开(公告)日：2008-08-07

    申请号：US12060922

    申请日：2008-04-02

    申请人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

    发明人： Toshijaru Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger ,  Chung H. Lam ,  Gerhard I. Meijer

    IPC分类号： H01L23/62 ,  H01L21/8234

    CPC分类号： H01L27/0629 ,  H01L27/101 ,  H01L27/24

    摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

    摘要翻译： 公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。 该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。 具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。 在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。