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公开(公告)号：US07526744B2
公开(公告)日：2009-04-28
申请号：US11669202
申请日：2007-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the set of routing definitions to locate and size conductors modeled in the mask data. A design tool includes a memory and a processor. The memory stores routing definitions that enable conductor routing schemes having the same cell pitch. The processor receives an input identifying a select routing definition from the set of routing definitions. The processor executes logic that generates an array of points responsive to a characteristic of the routing definitions. The processor further executes logic configured to constrain the relative location and width of conductors in the integrated circuit.
摘要翻译： 一种用于产生掩模数据的方法包括：接收一组路由定义，使得能够使用具有相同小区间距的导体路由方案，响应于该组的特征识别位置，呈现掩模数据的一部分的表示并应用选择成员 的路由定义集合来定位和定义在掩模数据中建模的导体。 设计工具包括内存和处理器。 存储器存储使得具有相同单元间距的导体路由方案的路由定义。 处理器从路由定义集合接收标识选择路由定义的输入。 处理器执行逻辑，其产生响应于路由定义的特性的点阵列。 处理器还执行配置成限制集成电路中导体的相对位置和宽度的逻辑。
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2.发明申请公开(公告)号：US20080184188A1
公开(公告)日：2008-07-31
申请号：US11669202
申请日：2007-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for generating mask data includes receiving a set of routing definitions that enable conductor routing schemes having the same cell pitch, identifying locations in response to a characteristic of the set, presenting a representation of a portion of the mask data and applying a select member of the set of routing definitions to locate and size conductors modeled in the mask data. A design tool includes a memory and a processor. The memory stores routing definitions that enable conductor routing schemes having the same cell pitch. The processor receives an input identifying a select routing definition from the set of routing definitions. The processor executes logic that generates an array of points responsive to a characteristic of the routing definitions. The processor further executes logic configured to constrain the relative location and width of conductors in the integrated circuit.
摘要翻译： 一种用于产生掩模数据的方法包括：接收一组路由定义，使得能够使用具有相同小区间距的导体路由方案，响应于该组的特征识别位置，呈现掩模数据的一部分的表示并应用选择成员 的路由定义集合来定位和定义在掩模数据中建模的导体。 设计工具包括内存和处理器。 存储器存储使得具有相同单元间距的导体路由方案的路由定义。 处理器从路由定义集合接收标识选择路由定义的输入。 处理器执行逻辑，其产生响应于路由定义的特性的点阵列。 处理器还执行配置成限制集成电路中导体的相对位置和宽度的逻辑。
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公开(公告)号：US06665218B2
公开(公告)日：2003-12-16
申请号：US10007603
申请日：2001-12-05
申请人： Peter J. Meier , Gerald L Esch, Jr.
发明人： Peter J. Meier , Gerald L Esch, Jr.
IPC分类号： G11C700
CPC分类号： H03L7/0812 , H04L7/0337
摘要： A self calibrating register. In representative embodiments, registers for increasing source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by programmed delays of the data signals. The appropriate delays are obtained via phase shift detection circuitry and are then applied by control circuitry to signal delay circuitry.
摘要翻译： 自校准寄存器。 在代表性实施例中，公开了通过抵消系统不匹配的固有系统源来增加源同步输入/输出（I / O）数据速率的寄存器。 位线路径和器件之间的系统不匹配的系统来源，例如印刷电路板路径长度，封装迹线长度，片上时钟路由，时钟偏移，器件导通电压等相对于 参考时钟信号由数据信号的编程延迟。 适当的延迟通过相移检测电路获得，然后由控制电路施加到信号延迟电路。
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公开(公告)号：US06744285B2
公开(公告)日：2004-06-01
申请号：US10215157
申请日：2002-08-08
申请人： Wayne G. Mangum , Brian C. Miller , Peter J. Meier , Cory Groth
发明人： Wayne G. Mangum , Brian C. Miller , Peter J. Meier , Cory Groth
IPC分类号： H03K906
CPC分类号： H04L7/0037 , G06F1/12 , H03K5/133 , H04L7/0012
摘要： A method and an apparatus for aligning the phases of clocks of different clock domains of an IC to enable data to be transferred synchronously across the clock domains. The present invention comprises a phase-alignment system that is adjustable via a user interface to enable the clock phases to be adjusted. A user controls the degree of alignment of the phases via the user interface. The present invention enables the phases of clocks of different clock domains to be adjusted even after the IC has been fabricated.
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公开(公告)号：US5646809A
公开(公告)日：1997-07-08
申请号：US520218
申请日：1995-08-28
IPC分类号： H01L21/8238 , H01L27/092 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/0948 , H02H9/00
CPC分类号： H03K19/00315
摘要： A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage.
摘要翻译： 提供高耐压CMOS输出驱动电路和高耐压CMOS输入接收电路，通过使用屏蔽晶体管和重新定义PFET器件的衬底。 本发明可以并入用于在具有较低电源电压的集成电路中的保护，而不是以较高电源电压工作的外部接口的器件。
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公开(公告)号：US20120250811A1
公开(公告)日：2012-10-04
申请号：US13076640
申请日：2011-03-31
申请人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
发明人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/081
摘要： A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.
摘要翻译： 时钟数据恢复系统和方法促进对输入数据信号中的大相位变化的快速调整。 该系统可以包括相位对准电路，时钟发生器电路，时间 - 数字转换器电路和采样电路。 相位对准电路使用输入数据信号和反馈时钟信号来产生输出时钟信号。 时钟发生器电路使用输出时钟信号来产生不同相位或极性的基相时钟信号。 时间 - 数字转换器电路使用基本相位时钟信号和输入数据信号来产生反馈时钟信号。 时基数字转换器电路将反馈时钟信号与基本相位时钟信号相比较，其基准相位时钟信号与输入的数据信号与其它基本相位时钟信号相比更紧密地对准。 采样电路使用一个或多个基本相位时钟信号重新计时或恢复数据信号。
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7.发明授权Integrated circuit design system and method for generating a regular structure embedded in a standard cell control block 失效用于生成嵌入在标准单元控制块中的规则结构的集成电路设计系统和方法
公开(公告)号：US5847969A
公开(公告)日：1998-12-08
申请号：US641660
申请日：1996-05-01
申请人： Brian C. Miller , Peter J. Meier
发明人： Brian C. Miller , Peter J. Meier
IPC分类号： G06F17/50 , H01L27/118 , G06F17/00
CPC分类号： H01L27/118 , G06F17/5068
摘要： An improved system and method are provided for generating a design for a regular structure such as a memory array, multiplier array, or adder array embedded in a standard cell control block (SCCB). Once a net list has been generated for the SCCB by a logic synthesis tool, a special class of cells is created for the elements of the regular structure. The net list is modified via a special class mechanism by adding to the cells of the special class one or more special properties that are designed to optimize the placement of the cells of the regular structure. A modified placement and routing tool processes the modified net list by reading and interpreting the special properties so as to generate an improved design for the SCCB.
摘要翻译： 提供了一种改进的系统和方法，用于产生常规结构的设计，例如嵌入在标准单元控制块（SCCB）中的存储器阵列，乘法器阵列或加法器阵列。 一旦通过逻辑综合工具为SCCB生成了网络列表，就会为常规结构的元素创建一个特殊类别的单元格。 通过向特殊类的单元格添加一个或多个专门用于优化常规结构单元格放置的特殊属性，可以通过特殊的类机制修改网络列表。 修改的布局和布线工具通过读取和解释特殊属性来处理修改的网络列表，以便为SCCB生成改进的设计。
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公开(公告)号：US08634503B2
公开(公告)日：2014-01-21
申请号：US13076640
申请日：2011-03-31
申请人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
发明人： Brian J. Misek , Robert K. Barnes , Peter J. Meier
IPC分类号： H04L27/00
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/081
摘要： A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.
摘要翻译： 时钟数据恢复系统和方法促进对输入数据信号中的大相位变化的快速调整。 该系统可以包括相位对准电路，时钟发生器电路，时间 - 数字转换器电路和采样电路。 相位对准电路使用输入数据信号和反馈时钟信号来产生输出时钟信号。 时钟发生器电路使用输出时钟信号来产生不同相位或极性的基相时钟信号。 时间 - 数字转换器电路使用基本相位时钟信号和输入数据信号来产生反馈时钟信号。 时基数字转换器电路将反馈时钟信号与基本相位时钟信号相比较，其基准相位时钟信号与输入的数据信号与其它基本相位时钟信号相比更紧密地对准。 采样电路使用一个或多个基本相位时钟信号重新计时或恢复数据信号。
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公开(公告)号：US06124869A
公开(公告)日：2000-09-26
申请号：US82172
申请日：1998-05-20
申请人： Brian C. Miller , Peter J. Meier
发明人： Brian C. Miller , Peter J. Meier
摘要： A method and apparatus for low cost set mapping in, for example, a computer graphics processor or communications device efficiently maps elements of one set into another set. When used in conjunction with a graphical display system the low cost set mapping logic enables a memory controller to efficiently communicate with a plurality of memory devices based upon a hierarchical computation scheme. The method and apparatus provide a pseudo-optimal mapping solution. By employing a pseudo-optimal mapping solution the low cost set mapping logic greatly reduces the computational resource required to perform the mapping operation.
摘要翻译： 在例如计算机图形处理器或通信设备中的用于低成本集映射的方法和装置有效地将一组的元素映射到另一组中。 当与图形显示系统一起使用时，低成本集映射逻辑使得存储器控制器能够基于分级计算方案与多个存储器设备有效地通信。 该方法和装置提供伪最优映射解决方案。 通过采用伪最优映射解决方案，低成本集映射逻辑大大降低了执行映射操作所需的计算资源。
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公开(公告)号：US5581197A
公开(公告)日：1996-12-03
申请号：US455473
申请日：1995-05-31
IPC分类号： H03K17/14 , H03K17/687 , H03K19/00 , H03K19/0175 , H03K19/0948 , H03K19/003
CPC分类号： H03K19/0005
摘要： The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature. Those exhibited variations are communicated by a current mirror to a gate voltage mirror that produces the complementary programming signals, and which themselves constitute negative feedback. The complementary current mirrors are of known of gain, which in conjunction with knowing the value of VDD, allows the determination in advance of a definite table of programming resistance values versus output impedances.
摘要翻译： CMOS输出驱动级中的输出阻抗由与常规上拉和下拉器件中的每一个串联的MOS器件的互补电流镜进行编程和补偿。 根据互补编程信号来控制这些额外的互补器件的导通，补偿编程信号被补偿制造工艺参数的变化以及温度变化。 P型编程信号可以参考+ VDD，并且由通过包括对称N型和P型FET串联的栅极电压反射镜的作用而由参考于GND的N型编程信号产生。 N型编程信号可以从伺服外部编程电压以跟踪内部产生的参考电压的反馈环路中使用的N型FET的栅极电压首先产生。 该栅极电压表现出反映由于工艺变化和温度导致的差异的变化。 那些显示的变化通过电流镜传送到产生互补编程信号的栅极电压镜，并且它们本身构成负反馈。 互补电流镜是已知的增益，其结合知道VDD的值，允许在编程电阻值与输出阻抗的确定表之前进行确定。
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