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    Method of forming isolated regions of oxide
    1.
    发明授权
    Method of forming isolated regions of oxide 失效
    形成氧化物隔离区的方法

    公开(公告)号：US5260229A

    公开(公告)日：1993-11-09

    申请号：US755508

    申请日：1991-08-30

    申请人： Robert L. Hodges ,  Frank R. Bryant ,  Fusen E. Chen ,  Che-Chia Wei

    发明人： Robert L. Hodges ,  Frank R. Bryant ,  Fusen E. Chen ,  Che-Chia Wei

    IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

    CPC分类号： H01L21/76202 ,  H01L21/32

    摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

    Poly-buffered LOCOS process
    2.
    发明授权
    Poly-buffered LOCOS process 失效
    多缓冲LOCOS过程

    公开(公告)号：US5506440A

    公开(公告)日：1996-04-09

    申请号：US270411

    申请日：1994-07-05

    申请人： Che-Chia Wei ,  Robert L. Hodges ,  Frank R. Bryant

    发明人： Che-Chia Wei ,  Robert L. Hodges ,  Frank R. Bryant

    IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L29/00 ,  H01L23/58

    CPC分类号： H01L21/32 ,  H01L21/76202

    摘要： A method is provided for forming an improved poly-buffered LOCOS process by forming a pad oxide layer over a substrate. A first nitride layer is formed over the pad oxide layer and a polysilicon layer is formed over the first nitride layer. A second nitride layer is formed over the polysilicon layer. An opening is etched through the second nitride layer, the polysilicon layer, the first nitride layer and the pad oxide layer to expose a portion of the underlying substrate. A field oxide region is then formed in the opening.

    摘要翻译： 提供了一种通过在衬底上形成衬垫氧化物层来形成改进的多缓冲LOCOS工艺的方法。 第一氮化物层形成在衬垫氧化物层上方，并且在第一氮化物层上形成多晶硅层。 在多晶硅层上形成第二氮化物层。 通过第二氮化物层，多晶硅层，第一氮化物层和焊盘氧化物层蚀刻开口以暴露下面的衬底的一部分。 然后在开口中形成场氧化物区域。

    Method of forming isolated regions of oxide
    3.
    发明授权
    Method of forming isolated regions of oxide 失效
    形成氧化物隔离区的方法

    公开(公告)号：US5977607A

    公开(公告)日：1999-11-02

    申请号：US447362

    申请日：1995-05-23

    申请人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

    发明人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

    IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L29/00

    CPC分类号： H01L21/32 ,  H01L21/76202

    摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

    摘要翻译： 提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成衬垫氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 然后在第一氮化硅层上形成多晶硅缓冲层。 在多晶硅层上形成第二氮化硅层。 在第二氮化硅层上形成并图案化光致抗蚀剂层。 通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。 至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。 在开口中蚀刻第一氮化硅层。 然后在开口中形成场氧化物区域。

    Semiconductor contact via structure having amorphous silicon side walls
    6.
    发明授权
    Semiconductor contact via structure having amorphous silicon side walls 失效
    具有非晶硅侧壁的半导体接触通孔结构

    公开(公告)号：US5317192A

    公开(公告)日：1994-05-31

    申请号：US879190

    申请日：1992-05-06

    申请人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

    发明人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/400

    CPC分类号： H01L23/5226 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.

    摘要翻译： 提供了一种用于形成集成电路接触结构的方法。 在半导体器件上形成导电区域。 此后，在导电区域上形成绝缘层。 然后通过绝缘区域形成到导电区域的开口。 薄的势垒层沉积在集成电路接触结构上。 通过反向溅射集成电路接触结构来去除薄势垒层的一部分，使得只有薄的阻挡侧壁保留。 最后，在集成电路接触结构上沉积导电金属层。 在一个实施例中，在沉积导电金属层之前烘烤集成电路接触结构。

    Semiconductor contact via structure and method
    8.
    发明授权
    Semiconductor contact via structure and method 失效
    半导体接触通过结构和方法

    公开(公告)号：US5444019A

    公开(公告)日：1995-08-22

    申请号：US157571

    申请日：1993-11-24

    申请人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

    发明人： Fusen E. Chen ,  Girish A. Dixit ,  Che-Chia Wei

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L23/5226 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

    摘要： A method is provided for forming an integrated circuit contact structure. A conductive region is formed on a semiconductor device. Thereafter an insulating layer is formed over the conductive region. An opening is then formed through the insulating region to the conductive region. A thin barrier layer is deposited over the integrated circuit contact structure. A portion of the thin barrier layer is removed by backsputtering the integrated circuit contact structure so that only a thin barrier sidewall remains. Finally, a conductive metal layer is deposited over the integrated circuit contact structure. In one embodiment, the integrated circuit contact structure is baked before the conductive metal layer is deposited.

    摘要翻译： 提供了一种用于形成集成电路接触结构的方法。 在半导体器件上形成导电区域。 此后，在导电区域上形成绝缘层。 然后通过绝缘区域形成到导电区域的开口。 薄的势垒层沉积在集成电路接触结构上。 通过反向溅射集成电路接触结构来去除薄势垒层的一部分，使得只有薄的阻挡侧壁保留。 最后，在集成电路接触结构上沉积导电金属层。 在一个实施例中，在沉积导电金属层之前烘烤集成电路接触结构。