利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

17 条记录 (耗时 0.023 秒)

    Method of forming isolated regions of oxide
    1.
    发明授权
    Method of forming isolated regions of oxide 失效
    形成氧化物隔离区的方法

    公开(公告)号：US5977607A

    公开(公告)日：1999-11-02

    申请号：US447362

    申请日：1995-05-23

    申请人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

    发明人： Robert Louis Hodges ,  Frank Randolph Bryant ,  Fusen E. Chen ,  Che-Chia Wei

    IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L29/00

    CPC分类号： H01L21/32 ,  H01L21/76202

    摘要： A method is provided for forming isolated regions of oxide of an integrated circuit, and an integrated circuit formed according to the same. A pad oxide layer is formed over a portion of a substrate. A first silicon nitride layer is formed over the pad oxide layer. A polysilicon buffer layer is then formed over the first silicon nitride layer. A second silicon nitride layer is formed over the polysilicon layer. A photoresist layer is formed and patterned over the second silicon nitride layer. An opening is etched through the second silicon nitride layer and the polysilicon buffer layer to expose a portion of the first silicon nitride layer. A third silicon nitride region is then formed on at least the polysilicon buffer layer exposed in the opening. The first silicon nitride layer is etched in the opening. A field oxide region is then formed in the opening.

    摘要翻译： 提供一种用于形成集成电路的隔离氧化物区域的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成衬垫氧化物层。 在衬垫氧化物层上形成第一氮化硅层。 然后在第一氮化硅层上形成多晶硅缓冲层。 在多晶硅层上形成第二氮化硅层。 在第二氮化硅层上形成并图案化光致抗蚀剂层。 通过第二氮化硅层和多晶硅缓冲层蚀刻开口以暴露第一氮化硅层的一部分。 至少在开口中暴露的多晶硅缓冲层上形成第三氮化硅区域。 在开口中蚀刻第一氮化硅层。 然后在开口中形成场氧化物区域。

    Method of fabricating planar regions in an integrated circuit
    2.
    发明授权
    Method of fabricating planar regions in an integrated circuit 失效
    在集成电路中制造平面区域的方法

    公开(公告)号：US5742095A

    公开(公告)日：1998-04-21

    申请号：US752749

    申请日：1996-11-20

    申请人： Frank Randolph Bryant ,  Robert Louis Hodges

    发明人： Frank Randolph Bryant ,  Robert Louis Hodges

    IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/314 ,  H01L21/32 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L29/51 ,  H01L29/78 ,  H01L23/58

    CPC分类号： H01L21/28176 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/32 ,  H01L21/76216 ,  H01L29/513 ,  H01L29/518

    摘要： A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.

    摘要翻译： 提供一种用于形成半导体集成电路的平面的方法和根据该集成电路形成的集成电路。 在硅衬底上形成栅氧化层。 在栅极氧化物层上形成第一多晶硅层，在第一多晶硅层上形成氮化物层。 然后对第一多晶硅和氮化物层进行构图和蚀刻，以形成露出栅极氧化物层的一部分的开口。 然后进行氧化步骤以在开口中形成场氧化物区域。 场氧化物区域形成为具有与第一多晶硅层的上表面大致平坦的上表面的厚度。 然后去除氮化物层，并对栅极氧化物和第一多晶硅层进行图案化和蚀刻以形成栅电极和互连。 可以在剩余的第一多晶硅区域和场氧化物层的一部分上形成硅化物或其它导电层，例如第二多晶硅层，以连接栅极和互连，因为第一多晶硅层的上表面基本上是平面的， 场氧化物区域的上表面并且不与场氧化物区域交叉。

    Integrated circuit transistor having drain junction offset
    4.
    发明授权
    Integrated circuit transistor having drain junction offset 失效
    具有漏极结偏移的集成电路晶体管

    公开(公告)号：US5729036A

    公开(公告)日：1998-03-17

    申请号：US523366

    申请日：1995-09-05

    申请人： Frank Randolph Bryant ,  Robert Louis Hodges

    发明人： Frank Randolph Bryant ,  Robert Louis Hodges

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

    CPC分类号： H01L29/66757 ,  H01L29/78624

    摘要： A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.

    摘要翻译： 制造集成电路晶体管的方法开始于在导电层上生长的绝缘层上形成栅电极。 侧壁间隔物沿着栅电极的垂直边缘形成，并且掩模施加到漏极区域。 然后将相对快速扩散的掺杂​​剂注入到导电层中的源极区域中。 此后，去除掩模，并用较慢扩散的掺杂​​剂注入漏区。 最后，导电层被退火，导致相对快速扩散的掺杂​​剂在源侧壁间隔物下方扩散到栅电极的源极侧的垂直边缘附近的位置，并使相对较慢的扩散掺杂剂在下面延伸 漏极侧壁间隔较小的距离，使得漏极结与栅极下方横向间隔开。 由于相对较慢扩散的掺杂​​剂和相对快速扩散的掺杂​​剂之间的扩散速率的差异，形成具有漏极结偏移的晶体管。

    Self-aligned gate and method
    6.
    发明授权
    Self-aligned gate and method 有权

    公开(公告)号：US06774001B2

    公开(公告)日：2004-08-10

    申请号：US09733243

    申请日：2000-12-07

    申请人： Robert Louis Hodges

    发明人： Robert Louis Hodges

    IPC分类号： H01L21336

    CPC分类号： H01L29/66583 ,  H01L21/26586 ,  H01L29/66537 ,  H01L29/66553

    摘要： A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers. Conventional fabrication operations define other structures to complete fabrication of an integrated circuit.

    Shallow trench isolation with thin nitride as gate dielectric
    8.
    发明授权
    Shallow trench isolation with thin nitride as gate dielectric 失效
    浅沟槽隔离采用薄氮化物作为栅极电介质

    公开(公告)号：US5952707A

    公开(公告)日：1999-09-14

    申请号：US986271

    申请日：1997-12-05

    申请人： Robert Louis Hodges

    发明人： Robert Louis Hodges

    IPC分类号： H01L21/28 ,  H01L21/762 ,  H01L29/51

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/76229 ,  H01L29/513 ,  H01L29/518

    摘要： A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top layer comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

    摘要翻译： 半导体结构包括第一导电类型的硅衬底，包括设置在其表面上的第二导电类型的阱和包括设置在表面上的氮化硅的介电层。 电介质层包括至少部分地设置在p阱上的开口。 电介质层还包括厚度小于10埃的包含二氧化硅的顶层。 具有与阱深度相当或更大的深度的沟槽延伸到开口内的衬底表面。 非导电材料设置在沟槽内并且具有与介电层基本上共面的上表面。 电介质层的一部分用作晶体管的栅极电介质。

    SRAM cell with p-channel pull-up sources connected to bit lines
    10.
    发明授权
    SRAM cell with p-channel pull-up sources connected to bit lines 失效
    具有p位上拉源的SRAM单元连接到位线

    公开(公告)号：US6011711A

    公开(公告)日：2000-01-04

    申请号：US775141

    申请日：1996-12-31

    申请人： Robert Louis Hodges ,  Frank Sigmund

    发明人： Robert Louis Hodges ,  Frank Sigmund

    IPC分类号： G11C11/412 ,  G11C11/00

    CPC分类号： G11C11/412

    摘要： A static random access memory cell comprising a storage latch having a first upper power supply voltage connection to a first bit line, a second upper power supply voltage connection to a second bit line, and a connection to a lower power supply voltage. A first access circuit connects the storage latch to the first bit line and a second access circuit connects the storage latch to the second bit line, wherein the storage latch is accessed utilizing the first access circuit and the second access circuit.

    摘要翻译： 一种静态随机存取存储单元，包括具有与第一位线的第一上电源电压连接的存储锁存器，到第二位线的第二上电源电压连接以及与较低电源电压的连接。 第一访问电路将存储锁存器连接到第一位线，而第二存取电路将存储锁存器连接到第二位线，其中使用第一存取电路和第二存取电路访问存储锁存器。