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公开(公告)号：US08611169B2
公开(公告)日：2013-12-17
申请号：US13315604
申请日：2011-12-09
申请人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
发明人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C8/08 , G11C8/10
摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.
摘要翻译： 描述了一种用于提供存储器阵列的精细粒度电源门控的方法。 在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。 激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线 存储器阵列中的剩余行被提供电源门控电压值。
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公开(公告)号：US20130148455A1
公开(公告)日：2013-06-13
申请号：US13315604
申请日：2011-12-09
申请人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
发明人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C8/08 , G11C8/10
摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.
摘要翻译： 描述了一种用于提供存储器阵列的精细粒度电源门控的方法。 在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。 激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线 存储器阵列中的剩余行被提供电源门控电压值。
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3.发明申请STRUCTURE FOR IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS 审中-公开用于改善半导体应用中的保险丝状态检测和电位的结构公开(公告)号：US20090153228A1
公开(公告)日：2009-06-18
申请号：US11958598
申请日：2007-12-18
申请人： John E. Barwin , Steven H. Lamphier , Harold Pilo
发明人： John E. Barwin , Steven H. Lamphier , Harold Pilo
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.
摘要翻译： 公开了一种装置的设计结构，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。 此外，公开了相关方法的实施例。 检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点 在未吹塑和最小吹塑电阻之间熔断熔断器。 因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。
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4.发明申请METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS 审中-公开改进半导体应用中保险丝状态检测和电位的方法公开(公告)号：US20080265982A1
公开(公告)日：2008-10-30
申请号：US12134260
申请日：2008-06-06
申请人： John E. Barwin , Steven H. Lamphier , Harold Pilo
发明人： John E. Barwin , Steven H. Lamphier , Harold Pilo
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.
摘要翻译： 公开了一种装置的实施例，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。 此外，公开了相关方法的实施例。 检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点 在未吹塑和最小吹塑电阻之间熔断熔断器。 因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。
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公开(公告)号：US06219288B1
公开(公告)日：2001-04-17
申请号：US09519392
申请日：2000-03-03
IPC分类号： G11C700
CPC分类号： G11C11/417 , G11C7/1045 , G11C7/22
摘要： A SRAM module provides programmability of AC timings such that an end user can adjust or “tweak” the AC timings to maximize system performance. A variable delay circuit is placed in the path between a signal (e.g., data signal or address signal)and the SRAM set-up and hold register which allows the user to shift the setup-and-hold window by selected increments. The delay circuit can either advance or retard the AC timings. A delay program controlling the delay circuit is selected in one of two ways; either by a default AC timing program stored in a ROM device and preset by the manufacturer, or by a private JTAG instruction and AC programming data input by the user through the JTAG state machine provided on the SRAM chip. Once the optimum delay (or advance) is selected to optimize the SRAM to the cache system this user program may be permanently burned into the default ROM such that the optimum timings are used thereafter as the default.
摘要翻译： SRAM模块提供AC定时的可编程性，使得最终用户可以调整或“调整”AC定时以最大化系统性能。 可变延迟电路被放置在信号（例如，数据信号或地址信号）和SRAM建立和保持寄存器之间的路径中，该寄存器允许用户按照选定的增量来移动建立和保持窗口。 延迟电路可以提前或延迟交流定时。 以两种方式之一选择控制延迟电路的延迟程序; 通过存储在ROM设备中并由制造商预设的默认AC定时程序，或通过由SRAM芯片上提供的JTAG状态机由用户输入的专用JTAG指令和AC编程数据。 一旦选择了最佳延迟（或提前）来优化到高速缓存系统的SRAM，该用户程序可以被永久地烧录到默认ROM中，使得此后使用最佳定时作为默认值。
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公开(公告)号：US5666078A
公开(公告)日：1997-09-09
申请号：US597655
申请日：1996-02-07
IPC分类号： H03K19/0185
CPC分类号： H03K19/018585
摘要： An output driver circuit is disclosed that generates an accurate and predictable output impedance driver value corresponding to a programmable external impedance. The output driver circuit includes an external resistance device, voltage comparator device, control logic, an evaluate circuit and off-chip driver (OCD) circuit. Voltage from the external resistance device (VZQ) is compared with voltage created from the evaluate circuit (VEVAL) by the voltage comparator device, which indicates to the control logic whether VEVAL is greater than or less than VZQ. The control logic will adjust the evaluate circuit accordingly with a count until the two voltages are basically equal (i.e., the count is alternating between two adjacent binary count values). At which time the control logic operates the OCD with the lower of the two adjacent count values to produce a proper and predictable driving impedance.
摘要翻译： 公开了一种输出驱动器电路，其产生对应于可编程外部阻抗的精确和可预测的输出阻抗驱动器值。 输出驱动电路包括外部电阻器件，电压比较器器件，控制逻辑器件，评估电路和片外驱动器（OCD）电路。 将来自外部电阻装置（VZQ）的电压与电压比较器装置从评估电路（VEVAL）产生的电压进行比较，该控制逻辑指示VEVAL是否大于或小于VZQ。 控制逻辑将根据计数相应地调整评估电路，直到两个电压基本相等（即计数在两个相邻的二进制计数值之间交替）。 此时，控制逻辑以两个相邻计数值的较低者操作OCD以产生适当且可预测的驱动阻抗。
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7.发明授权System and method for integrating dynamic leakage reduction with write-assisted SRAM architecture 有权将动态泄漏减少与写辅助SRAM架构相结合的系统和方法公开(公告)号：US07643357B2
公开(公告)日：2010-01-05
申请号：US12032798
申请日：2008-02-18
CPC分类号： G11C11/417
摘要： A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.
摘要翻译： 用于将动态泄漏减少与写辅助SRAM结构集成的系统包括与由一个或多个SRAM子阵列的每列相关联的电源线选择电路，由选择信号控制，选择信号选择相关联的子阵列进行读或写操作，以及 通过选择子阵列的列之一的列写入信号。 电源线选择电路将对应于用于读取操作的单元电源电压的第一电压本地转换为要提供给被选择用于写入操作的每个单元的第二较低电压，以便于写入功能。 电源线选择电路还将第一电压局部地转换为第三电压以提供给未选择的子阵列中的电力线，第三电压也低于第一电压，以便于动态泄漏降低。
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8.发明申请SYSTEM AND METHOD FOR INTEGRATING DYNAMIC LEAKAGE REDUCTION WITH WRITE-ASSISTED SRAM ARCHITECTURE 有权使用写辅助SRAM架构集成动态泄漏减少的系统和方法公开(公告)号：US20090207650A1
公开(公告)日：2009-08-20
申请号：US12032798
申请日：2008-02-18
CPC分类号： G11C11/417
摘要： A system for integrating dynamic leakage reduction with a write-assisted SRAM architecture includes power line selection circuitry associated with each column of one or more SRAM sub arrays, controlled by a selection signal that selects the associated sub array for a read or write operation, and by a column write signal that selects one of the columns of the sub arrays. The power line selection circuitry locally converts a first voltage, corresponding to a cell supply voltage for a read operation, to a second lower voltage to be supplied to each cell selected for a write operation, as to facilitate a write function. The power line selection circuitry also locally converts the first voltage to a third voltage to be supplied to power lines in unselected sub arrays, the third voltage also being lower than the first voltage so as to facilitate dynamic leakage reduction.
摘要翻译： 用于将动态泄漏减少与写辅助SRAM结构集成的系统包括与由一个或多个SRAM子阵列的每列相关联的电源线选择电路，由选择信号控制，选择信号选择相关联的子阵列进行读或写操作，以及 通过选择子阵列的列之一的列写入信号。 电源线选择电路将对应于用于读取操作的单元电源电压的第一电压本地转换为要提供给被选择用于写入操作的每个单元的第二较低电压，以便于写入功能。 电源线选择电路还将第一电压局部地转换为第三电压以提供给未选择的子阵列中的电力线，第三电压也低于第一电压，以便于动态泄漏降低。
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9.发明授权Method of improving fuse state detection and yield in semiconductor applications 有权提高半导体应用中熔丝状态检测和产量的方法公开(公告)号：US07403061B2
公开(公告)日：2008-07-22
申请号：US11277315
申请日：2006-03-23
申请人： John E. Barwin , Steven H. Lamphier , Harold Pilo
发明人： John E. Barwin , Steven H. Lamphier , Harold Pilo
IPC分类号： H01H37/76
CPC分类号： G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.
摘要翻译： 公开了一种装置的实施例，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。 此外，公开了相关方法的实施例。 检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点 在未吹塑和最小吹塑电阻之间熔断熔断器。 因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。
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10.发明申请Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译： 在制造的SRAM中设置字线上电压的方法。 在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。 然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。 提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。
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