公开(公告)号：US20090153228A1

公开(公告)日：2009-06-18

申请号：US11958598

申请日：2007-12-18

申请人： John E. Barwin ,  Steven H. Lamphier ,  Harold Pilo

发明人： John E. Barwin ,  Steven H. Lamphier ,  Harold Pilo

IPC分类号： H01H37/76 ,  G06F17/50

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

摘要翻译： 公开了一种装置的设计结构，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。 此外，公开了相关方法的实施例。 检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点 在未吹塑和最小吹塑电阻之间熔断熔断器。 因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。

公开(公告)号：US20080265982A1

公开(公告)日：2008-10-30

申请号：US12134260

申请日：2008-06-06

申请人： John E. Barwin ,  Steven H. Lamphier ,  Harold Pilo

发明人： John E. Barwin ,  Steven H. Lamphier ,  Harold Pilo

IPC分类号： H01H37/76

CPC分类号： G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

摘要翻译： 公开了一种装置的实施例，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。 此外，公开了相关方法的实施例。 检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点 在未吹塑和最小吹塑电阻之间熔断熔断器。 因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。

公开(公告)号：US07403061B2

公开(公告)日：2008-07-22

申请号：US11277315

申请日：2006-03-23

申请人： John E. Barwin ,  Steven H. Lamphier ,  Harold Pilo

发明人： John E. Barwin ,  Steven H. Lamphier ,  Harold Pilo

IPC分类号： H01H37/76

CPC分类号： G11C17/18 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

摘要翻译： 公开了一种装置的实施例，其包括适于确定所选保险丝的状态的检测电路和用于根据需要吹送选定保险丝的编程电路。 此外，公开了相关方法的实施例。 检测电路包括相同的信号和参考支路中的多个保险丝，以便增加用于检测熔断熔丝和/或电流源的信号余量，该熔断器和/或电流源被配置为使偏移电流通过信号和参考支路，以便设置用于检测的跳闸点 在未吹塑和最小吹塑电阻之间熔断熔断器。 因此，本发明提供具有比单面和差分熔丝状态检测装置更高灵敏度的单面熔丝状态检测装置的灵活性。

公开(公告)号：US07492199B2

公开(公告)日：2009-02-17

申请号：US11460638

申请日：2006-07-28

申请人： John E. Barwin ,  Harold Pilo

发明人： John E. Barwin ,  Harold Pilo

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/133

摘要： The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.

摘要翻译： 本发明提供一种构建延迟锁定环路时钟信号的方法，包括：向时钟信号分配器提供至少一个时钟信号; 在至少两个匹配的延迟线上交替地从时钟信号分离器输出至少一个时钟信号; 将所述至少两个匹配的延迟线中的每一个交替地传播所述时钟信号; 用控制信号指定每个匹配延迟线的延迟周期; 当固定的更新窗口总是存在于匹配的延迟线上时，用控制信号更新两个匹配的延迟线; 以及分配所述时钟信号以同步地更新所述至少两个匹配的延迟线，其中在所述匹配延迟线上的所述固定更新窗口中不存在转换。 从延迟线收集时钟脉冲输出并重建输入时钟的延迟版本。

公开(公告)号：US20080025447A1

公开(公告)日：2008-01-31

申请号：US11460638

申请日：2006-07-28

申请人： John E. Barwin ,  Harold Pilo

发明人： John E. Barwin ,  Harold Pilo

IPC分类号： H04L7/00

CPC分类号： H03L7/0814 ,  H03K5/133

摘要： The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.

摘要翻译： 本发明提供一种构建延迟锁定环路时钟信号的方法，包括：向时钟信号分配器提供至少一个时钟信号; 在至少两个匹配的延迟线上交替地从时钟信号分离器输出至少一个时钟信号; 将所述至少两个匹配的延迟线中的每一个交替地传播所述时钟信号; 用控制信号指定每个匹配延迟线的延迟周期; 当固定的更新窗口总是存在于匹配的延迟线上时，用控制信号更新两个匹配的延迟线; 以及分配所述时钟信号以同步地更新所述至少两个匹配的延迟线，其中在所述匹配延迟线上的所述固定更新窗口中不存在转换。 从延迟线收集时钟脉冲输出并重建输入时钟的延迟版本。

公开(公告)号：US08560990B2

公开(公告)日：2013-10-15

申请号：US12686457

申请日：2010-01-13

申请人： John E. Barwin ,  Jeanne P. S. Bickford

发明人： John E. Barwin ,  Jeanne P. S. Bickford

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

摘要翻译： 设计集成电路的方法包括基于至少一个可靠性约束来修改每个预定义电路的设计属性可变电迁移（EM）极限，以避免EM集成电路的违规。 该方法还包括使用每个预定义电路的经修改的设计变量EM限制将集成电路从高级描述合成到至少一个预定义电路装置的子集。

公开(公告)号：US08656325B2

公开(公告)日：2014-02-18

申请号：US13348850

申请日：2012-01-12

申请人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

发明人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/76 ,  G06F2217/78

摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。

公开(公告)号：US07057924B2

公开(公告)日：2006-06-06

申请号：US10758449

申请日：2004-01-15

申请人： Stefan Lammers ,  Hans-Heinrich Viehmann ,  Thomas M. Maffitt ,  John E. Barwin

发明人： Stefan Lammers ,  Hans-Heinrich Viehmann ,  Thomas M. Maffitt ,  John E. Barwin

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.

摘要翻译： 在开始磁存储单元的写入操作之前，MRAM器件的写入路径被预充电，增加写入操作的速度并减小写入周期时间。 参考线是预充电的，可以更好地控制字线和位线写入脉冲，从而缩短上升时间。 预充电时间可以隐藏在地址解码时间或冗余评估时间内。 本文还描述了用于全局参考电流发生器的电路设计。 还公开了一种快速接通电路，其增加对参考线预充电的速度。

公开(公告)号：US20130185684A1

公开(公告)日：2013-07-18

申请号：US13348850

申请日：2012-01-12

申请人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

发明人： John E. Barwin ,  Amol A. Joshi ,  Baozhen Li ,  Michael R. Ouellette

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/76 ,  G06F2217/78

摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。

公开(公告)号：US20110107291A1

公开(公告)日：2011-05-05

申请号：US12612909

申请日：2009-11-05

申请人： John E. Barwin ,  Nazmul Habib ,  Manikandan Viswanath

发明人： John E. Barwin ,  Nazmul Habib ,  Manikandan Viswanath

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths.

摘要翻译： 公开了允许在定时分析期间补偿区域时间变化的实施例，并且可选地允许优化关键路径的放置，作为这种区域时序变化的函数。 基于用于集成电路芯片的器件的初始放置，映射影响器件定时的一个或多个物理条件（例如，多晶硅周长密度，器件到阱边缘的平均距离，平均反射率）的区域变化。 然后，使用将不同降额因子与不同级别的物理条件相关联的表，将降额因子分配给地图上的不同区域。 接下来，进行定时分析，使得对于每个区域，该区域内的任何路径的延迟被降低了所指定的降额因子。 当在集成电路芯片上建立设备的最终放置以便优化关键路径的放置时，也可以使用地图信息。