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公开(公告)号：US06493315B1
公开(公告)日：2002-12-10
申请号：US08924060
申请日：1997-08-28
申请人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Vincent Cottignies , Pierre Dumas , David Mouen Makoua
发明人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Vincent Cottignies , Pierre Dumas , David Mouen Makoua
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/255 , H04L49/256 , H04L2012/563 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04Q11/0478
摘要： An ATM routing switch has a buffer circuit for holding cells located on queues at output ports, the buffer having a first reserve buffer capacity for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.
摘要翻译： ATM路由交换机具有用于保存位于输出端口上的队列上的小区的缓冲器电路，该缓冲器具有用于要求小区传输完整性的第一类型的小区的第一预备缓冲器容量，以及用于确定允许路径的第一指定 网络，具有用于确定网络中的不同允许路径的第二名称的第一类型的小区的第二预留缓冲器容量和用于接收传输中的小区的一些丢失的第二类型的小区的第三预留缓冲器容量，流控制 如果达到第一，第二或第三缓冲器容量的预定阈值，则操作以限制第一或第二类型的单元的输入的电路。
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公开(公告)号：US06229789B1
公开(公告)日：2001-05-08
申请号：US08919826
申请日：1997-08-28
申请人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
发明人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/255 , H04L49/309 , H04L2012/563 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04L2012/5681 , H04Q11/0478
摘要： An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.
摘要翻译： ATM路由交换机具有多个输出端口，用于处理需要信元传输完整性的第一类型的数字信号信元，以及接收传输中的小区的一些丢失的第二类型，所述输出端口具有控制电路以提供多个小区队列 在每个输出端口处，每个队列仅包括单一类型的单元，而每个端口在公共输出路径上输出两种类型的单元的混合，流入控制指示符用于阻止沿着到达目的地的任何路径的单元格的输出 流量控制指示器指示拥堵。
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公开(公告)号：US6021115A
公开(公告)日：2000-02-01
申请号：US919827
申请日：1997-08-28
申请人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
发明人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/3081 , H04Q11/0478 , H04L2012/563 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04L2012/5681
摘要： A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.
摘要翻译： ATM路由交换机的网络发送需要传输完整性的第一类型的数字信号小区，并且接收传输中的一些丢失的第二类型，每个交换机具有缓冲电路。 多个输出端口，每个输出端口具有等待输出的多个单元队列，每个输出端口具有控制电路，以在输出帧中提供控制指示小区类型的位，路径标识符和路由交换机上的流量拥塞的存在， 它输出该帧，从而阻止进一步的帧发送到该位置，直到从该位置接收到一个指示拥塞被清除的帧为止。
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公开(公告)号：US6144640A
公开(公告)日：2000-11-07
申请号：US920256
申请日：1997-08-28
申请人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
发明人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/255 , H04Q11/0478 , H04L2012/563 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04L2012/5681
摘要： An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.
摘要翻译： 用于至少两种类型的小区的双向传输的ATM路由交换机，接收可变比特率传输的一种类型和接收传输中的小区的一些丢失的第二类型，包括第一种类型的小区的第一预备缓冲器容量，第二种储备 如果通过所述第一类型的单元的输入达到用于第一缓冲器容量的预定阈值，则产生流控制信号（FCT）的所述第二类型的单元的缓冲器容量和控制电路，以及丢弃所述第二类型的输入单元，如果 通过输入所述第二类型的单元已经达到了所述第二缓冲器容量的预定阈值。
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公开(公告)号：US6128306A
公开(公告)日：2000-10-03
申请号：US919997
申请日：1997-08-28
申请人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
发明人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
IPC分类号： H04L12/54 , H04L12/70 , H04L12/931 , H04L12/933 , H04Q11/04 , H04L12/28
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/203 , H04Q11/0478 , H04L2012/563 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04L2012/5681
摘要： An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.
摘要翻译： ATM路由交换机具有多个输入和输出端口以及用于保存多个ATM信元的缓冲器，该单元作为多个队列保存在缓冲器中（F0-F7），每个队列形成为具有 前后指针标识每个队列的末端。
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公开(公告)号：US5987008A
公开(公告)日：1999-11-16
申请号：US919938
申请日：1997-08-28
申请人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
发明人： Robert Simpson , Neil Richards , Peter Thompson , Pascal Moniot , Marcello Coppola , Pierre Dumas , Thierry Grenot , David Mouen Makoua
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/3081 , H04Q11/0478 , H04L2012/563 , H04L2012/5647 , H04L2012/5649 , H04L2012/5651 , H04L2012/5681
摘要： An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.
摘要翻译： 一种用于双向传输数字信号单元的ATM路由交换机，一些需要传输完整性的数字信号单元，而另一些接收传输中的小区的一些丢失，具有多个输出端口，每个处理多个小区队列和用于解码每个输入单元中的控制位的控制电路 以确定要使用哪个输出端口，哪个队列是必需的，以及在输入单元的源头是否存在流量拥塞。
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公开(公告)号：US06480499B1
公开(公告)日：2002-11-12
申请号：US09413555
申请日：1999-10-06
IPC分类号： H04L1228
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： Apparatus for re-assembling information cells of messages, comprising a message memory, a message data memory, a location memory, and loading apparatus. The message memory stores each message in blocks that can be different lengths. The message data memory stores, for each message, message data defining a location in message memory, a position in the block, and a length of the block that is to receive the cells of the message. The location memory stores, for each message, an indication of the location of the message data. The loading apparatus receives the cells, and for each cell, accesses location memory to determine the location of message data, stores the cell in the message memory at the indicated location, increments the message data defining the location and the position, and compares the incremented position with the stored length of the block to determine whether the end of the block has been reached.
摘要翻译： 用于重组消息的信息单元的装置，包括消息存储器，消息数据存储器，位置存储器和加载装置。 消息存储器将每个消息以可以是不同长度的块存储。 消息数据存储器为每个消息存储定义消息存储器中的位置的消息数据，块中的位置以及要接收消息的单元的块的长度。 位置存储器针对每个消息存储消息数据的位置的指示。 加载设备接收单元，并且对于每个单元，访问位置存储器以确定消息数据的位置，将该单元存储在指示位置的消息存储器中，增加定义位置和位置的消息数据，并将增加的 位置与块的存储长度，以确定块的结束是否已到达。
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8.发明授权Reception of multiple data messages over a transmission medium with conversion into suitable form 有权通过传输介质接收多个数据消息，转换成合适的形式公开(公告)号：US06731097B1
公开(公告)日：2004-05-04
申请号：US09413419
申请日：1999-10-06
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5658 , H04L2012/5681
摘要： A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.
摘要翻译： 一种数据接收单元，用于通过数据信道接收多个数据流。 数据流被接收为数据量，每个数据量包括包括来自数据流的数据的数据部分和识别该数据流的标识部分。 数据接收单元包括包括多个数据流存储区域和预留缓冲器的数据流存储器，用于保存第一存储信息的第一存储信息存储器，处理单元和数据存储控制器。 数据存储控制器对于每个接收到的数据量，接收数据量的身份部分并且基于身份部分执行存储操作。
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9.发明授权Device for segmentation and transmission of messages stored as blocks of variable length 失效用于分段和传输存储为可变长度块的消息的设备公开(公告)号：US06614793B1
公开(公告)日：2003-09-02
申请号：US09412843
申请日：1999-10-06
IPC分类号： H04J324
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A data reception unit for receiving a plurality of data streams over a data chanel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation-based on the identity portion.
摘要翻译： 数据接收单元，用于通过数据通道接收多个数据流。 数据流被接收为数据量，每个数据量包括包括来自数据流的数据的数据部分和识别该数据流的标识部分。 数据接收单元包括包括多个数据流存储区域和预留缓冲器的数据流存储器，用于保存第一存储信息的第一存储信息存储器，处理单元和数据存储控制器。 数据存储控制器对于每个接收到的数据量，接收数据量的身份部分并且基于身份部分执行存储操作。
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公开(公告)号：US06970457B1
公开(公告)日：2005-11-29
申请号：US09413644
申请日：1999-10-06
CPC分类号： H04L12/5602 , H04L2012/5658 , H04L2012/5679 , H04Q11/0478
摘要： A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the data stream storage area corresponding to that data stream; and if the first storage information memory does not hold first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the escape buffer; and a processing unit connected to the escape buffer for performing an assembly operation comprising executing steps to assemble the information stored in the escape buffer into respective data streams.
摘要翻译： 一种数据接收单元，用于通过数据信道接收多个数据流，所述数据流被接收为数据量，并且每个数据量包括包括来自数据流的数据和识别该数据流的标识部分的数据部分， 数据接收单元，包括：数据流存储器，包括多个数据流存储区域，每个数据流存储区域用于存储来自一组数据流中的相应一个的数据;以及逃生缓冲器; 第一存储信息存储器，用于保存用于便于在数据流的集合中存储数据的相应数据流存储区域中的第一存储信息; 以及数据存储控制器，用于针对每个接收的数据量，接收所述数据量的身份部分并执行存储操作，包括：访问所述第一存储信息存储器; 并且如果所述第一存储信息存储器保存由所述身份部分识别的数据流的第一存储信息，则将所述数据量的数据部分存储在与所述数据流对应的数据流存储区域中; 并且如果所述第一存储信息存储器不存储由所述身份部分识别的数据流的第一存储信息，则将所述数据量的数据部分存储在所述转义缓冲器中; 以及处理单元，连接到逃逸缓冲器，用于执行组装操作，包括执行将存储在逃逸缓冲器中的信息组装成相应数据流的步骤。
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