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24 条记录 (耗时 0.031 秒)

    Buffer associated with multiple data communication channels
    7.
    发明授权
    Buffer associated with multiple data communication channels 有权
    与多个数据通信通道相关的缓冲区

    公开(公告)号：US06622186B1

    公开(公告)日：2003-09-16

    申请号：US09466508

    申请日：1999-12-17

    申请人： Pascal Moniot ,  Marcello Coppola

    发明人： Pascal Moniot ,  Marcello Coppola

    IPC分类号： G06F1300

    CPC分类号： H04Q11/0478 ,  G06F12/023 ,  G06F12/0875 ,  H04L49/103

    摘要： A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue. According to another embodiment, the partial queue stores a local image of a top portion of the main queue, and the memory controller exclusively uses the partial queue in assigning blocks to the chains of linked blocks. Further embodiments of the present invention provide methods of managing a buffer.

    摘要翻译： 提供了用于使数据流从输入通道适配到输出通道的缓冲器。 缓冲器包括以块为单位的DRAM，以及存储器控制器，用于管理块链接到链接块的链。 DRAM包含链接块链，与由一对输入和输出通道形成的每个通信通道相关联的数据，并且还包含用于列出未占用块的空闲块的主队列。 存储器控制器包括高速缓冲存储器，其包含存储器控制器在管理块分配中使用的空闲块的部分队列。 根据一个实施例，当部分队列的级别达到预定的最小限度时，高速缓冲存储器至少部分地由来自主队列的突发填充，并且当部分队列的级别达到预定的最大限制时，高速缓存存储器 至少部分地被突发排空到主队列中。 根据另一个实施例，部分队列存储主队列的顶部的本地图像，并且存储器控制器专门使用部分队列将块分配给链接块的链。 本发明的其他实施例提供了管理缓冲器的方法。

    System for transmitting data within a network between nodes of the network and flow control process for transmitting the data
    8.
    发明授权
    System for transmitting data within a network between nodes of the network and flow control process for transmitting the data 有权
    用于在网络节点之间的网络内传输数据的系统和用于发送数据的流量控制过程

    公开(公告)号：US07940788B2

    公开(公告)日：2011-05-10

    申请号：US12021004

    申请日：2008-01-28

    申请人： Michael Soulie ,  Riccardo Locatelli ,  Marcello Coppola

    发明人： Michael Soulie ,  Riccardo Locatelli ,  Marcello Coppola

    IPC分类号： H04L12/54

    CPC分类号： H04L47/10 ,  G06F15/7825 ,  H04L47/18 ,  H04L47/266 ,  H04L67/32

    摘要： A system is for transmitting data in a network and includes emitter nodes, each including a transmitter for transmitting requests for data transmission. The system may also include a receiver node receiving the data transmission from the emitter nodes and including a first memory for storing data transmitted by each emitter node, a second memory for storing the requests, and a transmitter. The data may be transmitted from the emitter nodes to the receiver node when memory space is available in the first memory to receive data. The transmitter of the receiver node may transmit to each emitter node an acknowledgement message when memory space is available in the first memory to receive at least a portion of the data transmitted. Each emitter node may establish a communication link with the receiver node and transmits the data based upon the acknowledgement message. The communication link may be locked until all data is transmitted.

    摘要翻译： 系统用于在网络中发送数据，并且包括发射器节点，每个发射器节点包括用于发送数据传输请求的发射机。 该系统还可以包括接收节点，其接收来自发射器节点的数据传输，并且包括用于存储由每个发射器节点发送的数据的第一存储器，用于存储请求的第二存储器和发射器。 当存储器空间在第一存储器中可用以接收数据时，数据可以从发射器节点传送到接收器节点。 当存储器空间在第一存储器中可用以接收所发送的数据的至少一部分时，接收机节点的发射机可以向每个发射节点传送确认消息。 每个发射器节点可以建立与接收机节点的通信链路，并根据确认消息发送数据。 可以锁定通信链路，直到发送所有数据。

    Buffering architecture for packet injection and extraction in on-chip networks
    10.
    发明授权
    Buffering architecture for packet injection and extraction in on-chip networks 有权
    片上网络中数据包注入和提取的缓冲架构

    公开(公告)号：US08165120B2

    公开(公告)日：2012-04-24

    申请号：US12291460

    申请日：2008-11-10

    申请人： Giuseppe Maruccia ,  Riccardo Locatelli ,  Lorenzo Pieralisi ,  Marcello Coppola

    发明人： Giuseppe Maruccia ,  Riccardo Locatelli ,  Lorenzo Pieralisi ,  Marcello Coppola

    IPC分类号： H04L12/56

    CPC分类号： H04L49/9063 ,  H04L49/3063 ,  H04L49/3072 ,  H04L49/90 ,  H04L49/9042

    摘要： This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.

    摘要翻译： 该方法用于通过芯片上的网络（NoC）在第一电子设备和第二电子设备之间传送数据，包括：从第一设备检索请求包括用于控制数据传送的请求控制数据和要传送的实际请求数据的分组; 将所述请求控制和要传送的数据存储在网络接口（NI）中提供的存储装置中; 并且通过所述网络详细描述要传送到第二设备的数据分组，所述数据分组包括分别从所述控制数据和所述实际数据详细描述的报头和有效载荷; 要传送的控制数据和实际数据被存储在单独的第一和第二存储装置中。