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    Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer
    1.
    发明授权
    Aggregate bandwidth through management using insertion of reset instructions for cache-to-cache data transfer 失效
    通过使用插入缓存到缓存数据传输的重置指令来管理带宽

    公开(公告)号：US07168070B2

    公开(公告)日：2007-01-23

    申请号：US10853304

    申请日：2004-05-25

    申请人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoging Gao ,  Randall Ray Heisch ,  Steven Wayne White

    发明人： Roch Georges Archambault ,  Robert James Blainey ,  Yaoging Gao ,  Randall Ray Heisch ,  Steven Wayne White

    IPC分类号： G06F9/45 ,  G06F13/00

    CPC分类号： G06F12/0833 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383

    摘要： A method and system for reducing or avoiding store misses with a data cache block zero (DCBZ) instruction in cooperation with the underlying hardware load stream prefetching support for helping to increase effective aggregate bandwith. The method identifies and classifies unique streams in a loop based on dependency and reuse analysis, and performs loop transformations, such as node splitting, loop distribution or stream unrolling to get the proper number of streams. Static prediction and run-time profile information are used to guide loop and stream selection. Compile-time loop cost analysis and run-time check code and versioning are used to determine the number of cache lines ahead of each reference for data cache line zeroing and to tolerate required data alignment relative to data cache lines.

    摘要翻译： 与底层硬件负载流预取支持协作，通过数据缓存块零（DCBZ）指令减少或避免存储错误的方法和系统，以帮助增加有效的聚合带宽。 该方法基于依赖和重用分析在循环中识别和分类唯一流，并执行循环转换，例如节点分割，循环分布或流展开以获得适当数量的流。 静态预测和运行时间轮廓信息用于指导循环和流选择。 编译时循环成本分析和运行时检查代码和版本控制用于确定数据高速缓存行归零的每个引用之前的高速缓存行数，并允许相对于数据高速缓存行的所需数据对齐。

    Optimizing source code for iterative execution
    5.
    发明授权
    Optimizing source code for iterative execution 有权
    优化源代码进行迭代执行

    公开(公告)号：US07340733B2

    公开(公告)日：2008-03-04

    申请号：US10314094

    申请日：2002-12-05

    申请人： Roch Georges Archambault ,  Robert James Blainey ,  Charles Brian Hall ,  Yingwei Zhang

    发明人： Roch Georges Archambault ,  Robert James Blainey ,  Charles Brian Hall ,  Yingwei Zhang

    IPC分类号： G06F9/44 ,  G06F9/45

    CPC分类号： G06F8/4441

    摘要： An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.

    摘要翻译： 本发明的一个实施例提供一种用于优化源代码以产生优化的源代码的优化器，其具有用于指示中央处理单元（CPU）迭代地计算初级重复元件的值的指令。 用于计算主要递归元素和随后的递归元素的计算机编程回路是涉及迭代地计算主要复发元素的情况的示例。 CPU可操作地耦合到快速操作存储器（FOM）并且可操作地耦合到慢速操作存储器（SOM）。 SOM存储生成的优化源代码。 优化的源代码包括用于指示所述CPU将计算的主循环元素的值存储在FOM的存储位置中的指令。 指令还包括将计算的主循环元素的值从存储位置委托给FOM的另一个存储位置的指令。

    Loop allocation for optimizing compilers
    6.
    发明授权
    Loop allocation for optimizing compilers 失效
    循环分配优化编译器

    公开(公告)号：US06651246B1

    公开(公告)日：2003-11-18

    申请号：US09574408

    申请日：2000-05-18

    申请人： Roch Georges Archambault ,  Robert James Blainey

    发明人： Roch Georges Archambault ,  Robert James Blainey

    IPC分类号： G06F945

    CPC分类号： G06F8/443

    摘要： Loop allocation for optimizing compilers includes the generation of a program dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to outermost, are generated and data dependence graph representations are generated for each level of nested loop as constrained by the control dependence graph. An interference graph is generated with the nodes of the data dependence graph. Weights are generated for the edges of the interference graph reflecting the affinity between statements represented by the nodes joined by the edges. Nodes in the interference graph are given weights reflecting resource usage by the statements associated with the nodes. The interference graph is partitioned using a profitability test based on the weights of edges and nodes and on a correctness test based on the reachability of nodes in the data dependence graph. Code is emitted based on the partitioned interference graph.

    摘要翻译： 用于优化编译器的循环分配包括生成源代码段的程序依赖图。 生成从最内到最外层的嵌套循环的控制依赖图表示，并且由控制依赖图约束的每个嵌套循环级生成数据依赖图表示。 使用数据依赖图的节点生成干涉图。 为干涉图的边缘生成反映由边缘连接的节点表示的语句之间的亲和度的权重。 干扰图中的节点被赋予反映与节点相关联的语句的资源使用权重。 使用基于边缘和节点的权重的利润率测试以及基于数据依赖图中的节点的可达性的正确性测试对干扰图进行分区。 基于分区干扰图发出代码。

    Code generation for complex arithmetic reduction for architectures lacking cross data-path support
    7.
    发明授权
    Code generation for complex arithmetic reduction for architectures lacking cross data-path support 有权
    针对缺乏跨数据路径支持的架构的复杂算术减少的代码生成

    公开(公告)号：US08423979B2

    公开(公告)日：2013-04-16

    申请号：US11548851

    申请日：2006-10-12

    申请人： Roch Georges Archambault ,  Alexandre E. Eichenberger ,  Amy Kai-Ting Wang ,  Peng Wu ,  Peng P. Zhao

    发明人： Roch Georges Archambault ,  Alexandre E. Eichenberger ,  Amy Kai-Ting Wang ,  Peng Wu ,  Peng P. Zhao

    IPC分类号： G06F9/45

    CPC分类号： G06F8/445 ,  G06F8/45

    摘要： A computer implemented method, apparatus, and computer usable program code for compiling source code for performing a complex operation followed by a complex reduction operation. A method is determined for generating executable code for performing the complex operation and the complex reduction operation. Executable code is generated for computing sub-products, reducing the sub-products to intermediate results, and summing the intermediate results to generate a final result in response to a determination that a reduced single instruction multiple data method is appropriate.

    摘要翻译： 一种计算机实现的方法，装置和计算机可用程序代码，用于编译用于执行复杂操作的复杂缩减操作的源代码。 确定用于生成用于执行复杂操作和复合缩减操作的可执行代码的方法。 生成用于计算子产品的可执行代码，将子产品减少到中间结果，并且对中间结果求和以响应于减少的单指令多数据方法的确定而产生最终结果。

    Sparse vectorization without hardware gather / scatter
    8.
    发明申请
    Sparse vectorization without hardware gather / scatter 失效
    稀疏矢量化无硬件收集/散射

    公开(公告)号：US20080092125A1

    公开(公告)日：2008-04-17

    申请号：US11549172

    申请日：2006-10-13

    申请人： Roch Georges Archambault ,  George Chochia ,  Peng Zhao

    发明人： Roch Georges Archambault ,  George Chochia ,  Peng Zhao

    IPC分类号： G06F9/45

    CPC分类号： G06F8/447

    摘要： A target operation in a normalized target loop, susceptible of vectorization and which may, after compilation into a vectorized form, seek to operate on data in nonconsecutive physical memory, is identified in source code. Hardware instructions are inserted into executable code generated from the source code, directing a system that will run the executable code to create a representation of the data in consecutive physical memory. A vector loop containing the target operation is replaced, in the executable code, with a function call to a vector library to call a vector function that will operate on the representation to generate a result identical to output expected from executing the vector loop containing the target operation. On execution, a representation of data residing in nonconsecutive physical memory is created in consecutive physical memory, and the vectorized target operation is applied to the representation to process the data.

    摘要翻译： 标准化目标循环中的目标操作，易于向量化，并且可以在编译成向量化形式之后寻求对非连续物理存储器中的数据进行操作，在源代码中被识别。 硬件指令被插入到从源代码生成的可执行代码中，指示将运行可执行代码的系统在连续的物理内存中创建数据的表示。 包含目标操作的向量循环在可执行代码中被替换为对向量库的函数调用，以调用将在表示上操作的向量函数，以生成与执行包含目标的向量循环所期望的输出相同的结果 操作。 在执行时，在连续物理存储器中创建驻留在非连续物理存储器中的数据的表示，并且向量化的目标操作被应用于表示以处理数据。

    Method and apparatus for optimizing software program using inter-procedural strength reduction
    9.
    发明授权
    Method and apparatus for optimizing software program using inter-procedural strength reduction 失效
    使用程序间强度降低优化软件程序的方法和装置

    公开(公告)号：US08146070B2

    公开(公告)日：2012-03-27

    申请号：US12270707

    申请日：2008-11-13

    申请人： Roch Georges Archambault ,  Shimin Cui ,  Raul Esteban Silvera

    发明人： Roch Georges Archambault ,  Shimin Cui ,  Raul Esteban Silvera

    IPC分类号： G06F9/45

    CPC分类号： G06F8/443

    摘要： Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations.

    摘要翻译： 通过本发明的机制来优化软件程序来提供程序间强度降低。 在正向通过期间，本发明收集全局变量的信息并分析该信息以选择用于优化的候选计算。 在反向传递期间，本发明使用预先计算的值替代使用成本较低或较弱计算的昂贵的计算，并插入新的全局变量的存储操作，以在昂贵的计算中使用的全局变量的定义点处预先计算昂贵的计算。