Abstract:
Cascade H-Bridge inverters and carrier-based level shift pulse width modulation techniques are presented for generating inverter stage switching control signals, in which carrier waveform levels are selectively shifted to control THD and to mitigate power distribution imbalances within multilevel inverter elements using either complementary carrier or complementary reference modulation techniques.
Abstract:
For transformer fault detection, a method generates a transition region that separates a health region and a fault region in a two-dimensional feature space of two feature indicators for a plurality of operation conditions using a fault detection model for a power transformer type. The method determines the feature indicators of a given power transformer of the power transformer type. The method determines whether the feature indicators in the transition region satisfy a fault condition. The method predicts an inter-turn short fault for the given power transformer in response to satisfying the fault condition or the feature indicators being in the fault region.
Abstract:
Cascade H-Bridge inverters and carrier-based level shift pulse width modulation techniques are presented for generating inverter stage switching control signals, in which carrier waveform levels are selectively shifted to control THD and to mitigate power distribution imbalances within multilevel inverter elements using either complementary carrier or complementary reference modulation techniques.
Abstract:
A component includes a power suspension module that suspends providing power from a DC source to a DC link capacitor and from the capacitor to a load. A bleeding resistor is connected in parallel with the capacitor and an auxiliary power supply draws power from the capacitor. The component includes a measurement module that measures a first, second and third capacitor voltage at a first, second, time, and third time in response suspending power between the DC source and the load. The component includes a capacitance module that uses bleeding resistor resistance, the voltages and the times to determine a current capacitance of the capacitor, a capacitance comparison module that compares the current capacitance with an initial capacitance of the capacitor, and an alert module that sends an alert in response to determining that a difference between the current capacitance and the initial capacitance is above a capacitance degradation threshold.
Abstract:
Power converters are presented with one or more sparse multilevel actively clamped (SMAC) power converter stages, where the individual stages include an integer number N capacitors or DC voltage sources coupled between stage DC inputs to provide L=N+1 converter stage DC voltage nodes, with a switching circuit having no more than L*(L−1) switching devices and no flying or floating DC storage capacitors, where N is greater than 2.
Abstract:
Cascade H-Bridge inverters and carrier-based level shift pulse width modulation techniques are presented for generating inverter stage switching control signals, in which carrier waveform levels are selectively shifted to control THD and to mitigate power distribution imbalances within multilevel inverter elements using either complementary carrier or complementary reference modulation techniques.
Abstract:
Power conversion systems, control apparatus, methods and computer readable mediums to operate a multiphase multilevel inverter that includes M inverter phase leg circuits that individually include N inverter stages with corresponding stage outputs connected in series between a reference node and a corresponding inverter phase output node, M being greater than 2, N being greater than 2, in which the stage outputs of a selected set of M of the inverter stages are bypassed, where the selected set includes a single inverter stage from each of the inverter phase leg circuits, and the selected set of inverter stages are connected to secondaries of a phase shift transformer at M different phase relationships to control harmonic distortion in a current of the transformer primary in response to a suspected inverter stage fault.
Abstract:
Power converters are presented with one or more sparse multilevel actively clamped (SMAC) power converter stages, where the individual stages include an integer number N capacitors or DC voltage sources coupled between stage DC inputs to provide L=N+1 converter stage DC voltage nodes, with a switching circuit having no more than L*(L−1) switching devices and no flying or floating DC storage capacitors, where N is greater than 2.
Abstract translation:功率转换器具有一个或多个稀疏多电平有源钳位(SMAC)功率转换器级,其中各个级包括耦合在级DC输入之间的整数N个电容器或DC电压源,以提供L = N + 1个转换器级DC电压节点 ,具有不超过L *(L-1)个开关装置的开关电路,并且没有飞行或浮动的直流存储电容器,其中N大于2。
Abstract:
Power converters and control techniques are presented in which capacitor degradation is detected according to negative sequence current by computing an uncompensated negative sequence current and a negative sequence voltage, compensating the negative sequence current based on the negative sequence voltage, comparing the compensated or uncompensated negative sequence current with an automatically calculated threshold and selectively identifying suspected degradation of one or more capacitors if the compensated negative sequence current exceeds the threshold value. The method can be used for power converters, control devices or protection relays for shunt capacitors or filters used in power systems.