公开(公告)号：US06701387B1

公开(公告)日：2004-03-02

申请号：US09652644

申请日：2000-08-31

申请人： Roger Pannel ,  David W. Hartwell ,  Samuel H. Duncan ,  Rajen Ramchandani ,  Andrej Kocev ,  Jeffrey Willcox ,  Steven Ho

发明人： Roger Pannel ,  David W. Hartwell ,  Samuel H. Duncan ,  Rajen Ramchandani ,  Andrej Kocev ,  Jeffrey Willcox ,  Steven Ho

IPC分类号： G06F1300

CPC分类号： G06F12/0862 ,  G06F13/28

摘要： A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

摘要翻译： 一种用于通过DMA连接到多处理器系统网格的PCI协议I / O设备来适应DMA读请求的速度要求的方法和装置。 描述了设备控制器和网格之间的桥接器，其将来自数据的数据的缓存行中的数据从数据缓存到I / O设备。 该系统是自适应的，因为过去读取中所需的高速缓存行的数量被记住并用于确定高速缓存行的数量是减少还是增加。

公开(公告)号：US07099978B2

公开(公告)日：2006-08-29

申请号：US10662782

申请日：2003-09-15

申请人： Samuel H. Duncan ,  Andrej Kocev ,  David T. Mayo

发明人： Samuel H. Duncan ,  Andrej Kocev ,  David T. Mayo

IPC分类号： G06F13/32 ,  G06F13/24

CPC分类号： G06F13/24 ,  G06F2213/0024

摘要： A method and system for completing pending I/O device reads by periodically stalling the issuance of I/O device accesses by a program in a multiple-processor computer system.

摘要翻译： 一种用于通过在多处理器计算机系统中的程序周期性地停止I / O设备访问的发布来完成未完成的I / O设备读取的方法和系统。

公开(公告)号：US06920516B2

公开(公告)日：2005-07-19

申请号：US09944516

申请日：2001-08-31

申请人： David W. Hartwell ,  Samuel H. Duncan ,  David T. Mayo ,  David J. Golden

发明人： David W. Hartwell ,  Samuel H. Duncan ,  David T. Mayo ,  David J. Golden

IPC分类号： G06F13/24 ,  G06F13/40 ,  H03K5/19

CPC分类号： H03K5/19 ,  G06F13/24 ,  G06F13/4081 ,  G06F2213/2402

摘要： An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR. In response, the processor copies all of the pending interrupts from the first CSR into the memory subsystem, thereby freeing up the first CSR to accept additional write transactions.

摘要翻译： 提供了一种用于避免多处理器计算机系统中的活动锁定的反饥饿中断协议。 至少一个处理器被配置为包括第一和第二控制状态寄存器（CSR）。 第一个CSR缓冲器由处理器接收到的中断信息，而第二个CSR跟踪中断的优先级。 当中断控制器接收到中断时，它会在处理器发出写入事务给第一个CSR。 如果第一个CSR有空间接受写入事务，则处理器返回确认，而如果第一个CSR已经满，则处理器返回一个无确认。 响应于无应答，中断控制器增加中断饥饿计数器，并检查计数器是否超过阈值。 如果没有，则中断控制器等待预设时间并转发写入事务。 如果是这样，中断控制器向第二个CSR发出具有较高优先级的写入事务。 作为响应，处理器将来自第一CSR的所有待处理中断复制到存储器子系统中，从而释放第一个CSR以接受额外的写事务。

公开(公告)号：US06738836B1

公开(公告)日：2004-05-18

申请号：US09652391

申请日：2000-08-31

申请人： Richard E. Kessler ,  Samuel H. Duncan ,  David W. Hartwell ,  David A. J. Webb, Jr. ,  Steve Lang

发明人： Richard E. Kessler ,  Samuel H. Duncan ,  David W. Hartwell ,  David A. J. Webb, Jr. ,  Steve Lang

IPC分类号： G06F1300

CPC分类号： G06F15/17381 ,  G06F12/0817 ,  G06F2212/621

摘要： A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.

摘要翻译： 公开了一种支持高性能，可扩展和高效的I / O端口协议来连接到I / O设备的系统。 分布式多处理计算机系统包含多个处理器，每个处理器都耦合到实现I / O端口协议的I / O桥ASIC。 一个或多个I / O设备耦合到I / O桥ASIC，每个I / O设备能够通过发送和接收消息分组来访问计算机系统中的机器资源。 计算机系统中的机器资源包括数据块，寄存器和中断队列。 计算机系统中的每个处理器耦合到能够存储处理器之间共享的数据块的存储器模块。 使用基于目录的一致性协议来维护该共享存储器系统中的共享数据块的一致性。 使用与存储系统相同的一致性协议来维护I / O设备读写访问期间传输的数据块的一致性。 只有当I / O桥ASIC具有数据块的排他副本时，I / O桥ASIC才能缓存在I / O设备读或写访问期间传输的数据块。 I / O桥ASIC包括支持数据块的顺序和无序DMA读和写数据流的DMA设备。 由DMA设备执行的数据块的顺序读取流总是导致DMA设备接收不必写入存储器模块的相干数据块。

公开(公告)号：US06826653B2

公开(公告)日：2004-11-30

申请号：US10068427

申请日：2002-02-06

申请人： Samuel H. Duncan ,  Frederick C. Canter ,  Darrel D. Donaldson ,  David W. Hartwell

发明人： Samuel H. Duncan ,  Frederick C. Canter ,  Darrel D. Donaldson ,  David W. Hartwell

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F2212/621

摘要： A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a “source” partition and to store that information within its own “destination” partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover “valid”, but non-coherent copy of the information, e.g., a “snapshot” of the information as of the time of the request. Upon receiving the information, the data mover may copy it into the memory subsystem of the destination partition.

摘要翻译： 提供了一种系统和方法，用于在分区多处理器计算机系统的高速缓存一致存储器系统之间移动信息，同时将故障包含在单个分区中。 多处理器计算机系统包括可以被分成多个分区的多个处理器，存储器子系统和输入/输出（I / O）子系统。 每个I / O子系统包括用于在一个或多个I / O设备和多处理器系统之间进行接口的至少一个I / O桥。 I / O网桥具有数据移动设备，用于从“源”分区检索信息，并将该信息存储在其自己的“目标”分区中。 当激活时，数据移动器向源分区发出请求，以获得不相干的信息副本。 源分区中的家用存储器子系统优选地通过发送数据移动器“有效”但是信息的非相干副本（例如，请求的时间的信息的“快照”）来响应该请求。 一旦接收到该信息，数据移动器可将其复制到目的地分区的存储子系统中。

公开(公告)号：US08364851B2

公开(公告)日：2013-01-29

申请号：US10677583

申请日：2003-10-02

申请人： Richard E. Kessler ,  Samuel H. Duncan ,  David W. Hartwell ,  David A. J. Webb, Jr. ,  Steve Lang

发明人： Richard E. Kessler ,  Samuel H. Duncan ,  David W. Hartwell ,  David A. J. Webb, Jr. ,  Steve Lang

IPC分类号： G06F3/00

CPC分类号： G06F15/17381 ,  G06F12/0817 ,  G06F2212/621

摘要： A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system. Data blocks transferred during an I/O device read or write access may be buffered in a cache by the I/O bridge ASIC only if the I/O bridge ASIC has exclusive copies of the data blocks. The I/O bridge ASIC includes a DMA device that supports both in-order and out-of-order DMA read and write streams of data blocks. An in-order stream of reads of data blocks performed by the DMA device always results in the DMA device receiving coherent data blocks that do not have to be written back to the memory module.

摘要翻译： 公开了一种支持高性能，可扩展和高效的I / O端口协议来连接到I / O设备的系统。 分布式多处理计算机系统包含多个处理器，每个处理器都耦合到实现I / O端口协议的I / O桥ASIC。 一个或多个I / O设备耦合到I / O桥ASIC，每个I / O设备能够通过发送和接收消息分组来访问计算机系统中的机器资源。 计算机系统中的机器资源包括数据块，寄存器和中断队列。 计算机系统中的每个处理器耦合到能够存储处理器之间共享的数据块的存储器模块。 使用基于目录的一致性协议来维护该共享存储器系统中的共享数据块的一致性。 使用与存储系统相同的一致性协议来维护I / O设备读写访问期间传输的数据块的一致性。 只有当I / O桥ASIC具有数据块的排他副本时，I / O桥ASIC才能缓存在I / O设备读或写访问期间传输的数据块。 I / O桥ASIC包括支持数据块的顺序和无序DMA读和写数据流的DMA设备。 由DMA设备执行的数据块的顺序读取流总是导致DMA设备接收不必写入存储器模块的相干数据块。

公开(公告)号：US07024509B2

公开(公告)日：2006-04-04

申请号：US09944515

申请日：2001-08-31

申请人： Samuel H. Duncan ,  Steven Ho

发明人： Samuel H. Duncan ,  Steven Ho

IPC分类号： G06F13/36

CPC分类号： H03K5/19 ,  G06F13/24 ,  G06F13/4081 ,  G06F2213/2402

摘要： A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled. After forwarding the first message to the I/O device, the bridge port forwards the second message to the interrupt controller so that the interrupt can be deasserted before the interrupt pending flag is cleared.

公开(公告)号：US06647453B1

公开(公告)日：2003-11-11

申请号：US09652984

申请日：2000-08-31

申请人： Samuel H. Duncan ,  Steven Ho

发明人： Samuel H. Duncan ,  Steven Ho

IPC分类号： G06F1336

CPC分类号： G06F12/0835

摘要： A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

摘要翻译： 一种系统和方法避免了竞争相同数据的对称多处理器（SMP）计算机系统的两个或多个输入/输出（I / O）设备中的“活动锁定”和“饥饿”。 SMP计算机系统包括多个互连处理器，由处理器共享的一个或多个存储器以及I / O设备耦合到的多个I / O桥。 执行缓存一致性协议的I / O网桥，这需要I / O网桥获得由桥接器存储的所有数据的“独占”（非共享）所有权。 响应于对I / O桥当前存储的数据的请求，桥接器首先在将数据无效之前将该数据的至少一部分复制到非相干缓冲器。 然后，桥接器保存在其非相干缓冲器中的最大数量的数据，其被认为是相干的，并且仅将已知的相干量释放到I / O设备，然后丢弃所有保存的数据。

公开(公告)号：US06832282B2

公开(公告)日：2004-12-14

申请号：US10611569

申请日：2003-07-01

申请人： Samuel H. Duncan ,  Steven Ho

发明人： Samuel H. Duncan ,  Steven Ho

IPC分类号： G06F1336

CPC分类号： G06F12/0835

摘要： A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

摘要翻译： 一种系统和方法避免了竞争相同数据的对称多处理器（SMP）计算机系统的两个或多个输入/输出（I / O）设备中的“活动锁定”和“饥饿”。 SMP计算机系统包括多个互连处理器，由处理器共享的一个或多个存储器以及I / O设备耦合到的多个I / O桥。 执行缓存一致性协议的I / O网桥，这需要I / O网桥获得由桥接器存储的所有数据的“独占”（非共享）所有权。 响应于对I / O桥当前存储的数据的请求，桥接器首先在将数据无效之前将该数据的至少一部分复制到非相干缓冲器。 然后，桥接器保存在其非相干缓冲器中的最大数量的数据，其被认为是相干的，并且仅将已知的相干量释放到I / O设备，然后丢弃所有保存的数据。

公开(公告)号：US09442759B2

公开(公告)日：2016-09-13

申请号：US13316334

申请日：2011-12-09

申请人： Samuel H. Duncan ,  Lacky V. Shah ,  Sean J. Treichler ,  Daniel Elliot Wexler ,  Jerome F. Duluk, Jr. ,  Philip Browning Johnson ,  Jonathon Stuart Ramsay Evans

发明人： Samuel H. Duncan ,  Lacky V. Shah ,  Sean J. Treichler ,  Daniel Elliot Wexler ,  Jerome F. Duluk, Jr. ,  Philip Browning Johnson ,  Jonathon Stuart Ramsay Evans

IPC分类号： G06F9/46 ,  G06F13/00 ,  G06F9/48 ,  G06F9/38

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/461

摘要： A time slice group (TSG) is a grouping of different streams of work (referred to herein as “channels”) that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units.

摘要翻译： 时间片组（TSG）是共享相同上下文信息的不同工作流（本文称为“信道”）的分组。 属于TSG的信道集合以预定的顺序被处理。 然而，当通道在处理过程中停顿时，可以切换具有独立工作的下一个通道来完全加载并行处理单元。 重要的是，由于TSG中的每个信道共享相同的上下文信息，当TSG中的特定信道的处理停止并且TSG中的下一个信道的处理开始时，不需要上下文切换操作。 因此，允许多个独立的工作流在单个上下文中同时运行，增加并行处理单元的利用率。