公开(公告)号：US06701387B1

公开(公告)日：2004-03-02

申请号：US09652644

申请日：2000-08-31

申请人： Roger Pannel ,  David W. Hartwell ,  Samuel H. Duncan ,  Rajen Ramchandani ,  Andrej Kocev ,  Jeffrey Willcox ,  Steven Ho

发明人： Roger Pannel ,  David W. Hartwell ,  Samuel H. Duncan ,  Rajen Ramchandani ,  Andrej Kocev ,  Jeffrey Willcox ,  Steven Ho

IPC分类号： G06F1300

CPC分类号： G06F12/0862 ,  G06F13/28

摘要： A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

摘要翻译： 一种用于通过DMA连接到多处理器系统网格的PCI协议I / O设备来适应DMA读请求的速度要求的方法和装置。 描述了设备控制器和网格之间的桥接器，其将来自数据的数据的缓存行中的数据从数据缓存到I / O设备。 该系统是自适应的，因为过去读取中所需的高速缓存行的数量被记住并用于确定高速缓存行的数量是减少还是增加。

公开(公告)号：US06832282B2

公开(公告)日：2004-12-14

申请号：US10611569

申请日：2003-07-01

申请人： Samuel H. Duncan ,  Steven Ho

发明人： Samuel H. Duncan ,  Steven Ho

IPC分类号： G06F1336

CPC分类号： G06F12/0835

摘要： A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

摘要翻译： 一种系统和方法避免了竞争相同数据的对称多处理器（SMP）计算机系统的两个或多个输入/输出（I / O）设备中的“活动锁定”和“饥饿”。 SMP计算机系统包括多个互连处理器，由处理器共享的一个或多个存储器以及I / O设备耦合到的多个I / O桥。 执行缓存一致性协议的I / O网桥，这需要I / O网桥获得由桥接器存储的所有数据的“独占”（非共享）所有权。 响应于对I / O桥当前存储的数据的请求，桥接器首先在将数据无效之前将该数据的至少一部分复制到非相干缓冲器。 然后，桥接器保存在其非相干缓冲器中的最大数量的数据，其被认为是相干的，并且仅将已知的相干量释放到I / O设备，然后丢弃所有保存的数据。

公开(公告)号：US06647453B1

公开(公告)日：2003-11-11

申请号：US09652984

申请日：2000-08-31

申请人： Samuel H. Duncan ,  Steven Ho

发明人： Samuel H. Duncan ,  Steven Ho

IPC分类号： G06F1336

CPC分类号： G06F12/0835

摘要： A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

摘要翻译： 一种系统和方法避免了竞争相同数据的对称多处理器（SMP）计算机系统的两个或多个输入/输出（I / O）设备中的“活动锁定”和“饥饿”。 SMP计算机系统包括多个互连处理器，由处理器共享的一个或多个存储器以及I / O设备耦合到的多个I / O桥。 执行缓存一致性协议的I / O网桥，这需要I / O网桥获得由桥接器存储的所有数据的“独占”（非共享）所有权。 响应于对I / O桥当前存储的数据的请求，桥接器首先在将数据无效之前将该数据的至少一部分复制到非相干缓冲器。 然后，桥接器保存在其非相干缓冲器中的最大数量的数据，其被认为是相干的，并且仅将已知的相干量释放到I / O设备，然后丢弃所有保存的数据。

公开(公告)号：US07024509B2

公开(公告)日：2006-04-04

申请号：US09944515

申请日：2001-08-31

申请人： Samuel H. Duncan ,  Steven Ho

发明人： Samuel H. Duncan ,  Steven Ho

IPC分类号： G06F13/36

CPC分类号： H03K5/19 ,  G06F13/24 ,  G06F13/4081 ,  G06F2213/2402

摘要： A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled. After forwarding the first message to the I/O device, the bridge port forwards the second message to the interrupt controller so that the interrupt can be deasserted before the interrupt pending flag is cleared.

公开(公告)号：US5202973A

公开(公告)日：1993-04-13

申请号：US546548

申请日：1990-06-29

申请人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

发明人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

IPC分类号： G06F13/16 ,  G06F13/376

CPC分类号： G06F13/161 ,  G06F13/376

摘要： A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.

摘要翻译： 用于控制多处理器系统的计算机中的共享存储器总线的系统和方法防止共享总线上的冲突，并确保总线在系统启动时已满。 维持稳定状态操作，而不需要系统存储器控制器中的排队机制，并且考虑到具有不同读取访问时间的共享存储器的存储器模块，系统和方法在包括中央单元和 多个单向总线设置在共享存储器和多个处理器之间，中央单元控制对系统的共享总线的访问和使用。

公开(公告)号：US20120301919A1

公开(公告)日：2012-11-29

申请号：US13479756

申请日：2012-05-24

申请人： Yuansheng Yang ,  Steven Ho ,  Jia Juan Lee

发明人： Yuansheng Yang ,  Steven Ho ,  Jia Juan Lee

IPC分类号： C12N15/63 ,  C12N15/52 ,  C12N15/53 ,  C12N15/54 ,  C12N15/62 ,  C12P21/02 ,  C12N15/13 ,  C12N9/08 ,  C12N9/02 ,  C12N9/12 ,  C12N9/00 ,  C12N1/21 ,  C12N1/19 ,  C12N1/15 ,  C12N5/10 ,  C12N5/16 ,  C12N15/11

CPC分类号： C12N15/67 ,  C12N15/85 ,  C12N2840/203 ,  C12N2840/206 ,  C12P21/02

摘要： This invention relates to nucleic acid molecules comprising at least one nucleic acid sequence encoding for a peptide or protein of interest, at least one nucleic acid sequence encoding for a selectable marker, and at least one IRES sequence, wherein the at least one IRES sequence is located between the at least one nucleic acid sequence encoding for the peptide or protein of interest and the at least one nucleic acid sequence encoding for the selectable marker. Furthermore, this invention relates to host cells comprising such nucleic acid molecule and to methods of recombinant protein expression using such host cells.

摘要翻译： 本发明涉及包含至少一个编码目标肽或蛋白质的核酸序列的核酸分子，至少一个编码选择标记的核酸序列和至少一个IRES序列，其中至少一个IRES序列是 位于至少一个编码目标肽或蛋白质的核酸序列和至少一个编码可选择标记的核酸序列之间。 此外，本发明涉及包含这种核酸分子的宿主细胞和涉及使用这种宿主细胞的重组蛋白表达的方法。

公开(公告)号：US5319678A

公开(公告)日：1994-06-07

申请号：US854519

申请日：1992-03-20

申请人： Steven Ho ,  Niamh Darcy

发明人： Steven Ho ,  Niamh Darcy

IPC分类号： G06F13/42 ,  H04L7/02 ,  H04L7/00

CPC分类号： G06F13/4217 ,  H04L7/02

摘要： A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.

摘要翻译： 连接到总线的模块中的时钟机制，在其上执行异步操作，其中产生时钟脉冲，其可以对数据的传输或捕获进行定时以及确认或同步线的转换。 每个时钟机制基于与同步或确认总线相关联的信号的接收来产生其时钟脉冲。 时钟机构包括多路复用器，其向可重置锁存器提供与所选行的条件相关联的信号。 可复位锁存器与延迟元件一起产生时钟脉冲。

公开(公告)号：US08809017B2

公开(公告)日：2014-08-19

申请号：US13479756

申请日：2012-05-24

申请人： Yuansheng Yang ,  Steven Ho ,  Jia Juan Lee

发明人： Yuansheng Yang ,  Steven Ho ,  Jia Juan Lee

IPC分类号： C12P21/06 ,  C12P1/00 ,  C12P21/04 ,  C12N5/02 ,  C12N5/07 ,  C12N15/00 ,  C07H21/04

CPC分类号： C12N15/67 ,  C12N15/85 ,  C12N2840/203 ,  C12N2840/206 ,  C12P21/02

摘要： This invention relates to nucleic acid molecules comprising at least one nucleic acid sequence encoding for a peptide or protein of interest, at least one nucleic acid sequence encoding for a selectable marker, and at least one IRES sequence, wherein the at least one IRES sequence is located between the at least one nucleic acid sequence encoding for the peptide or protein of interest and the at least one nucleic acid sequence encoding for the selectable marker. Furthermore, this invention relates to host cells comprising such nucleic acid molecule and to methods of recombinant protein expression using such host cells.

摘要翻译： 本发明涉及包含至少一个编码目标肽或蛋白质的核酸序列的核酸分子，至少一个编码选择标记的核酸序列和至少一个IRES序列，其中至少一个IRES序列是 位于至少一个编码目标肽或蛋白质的核酸序列和至少一个编码可选择标记的核酸序列之间。 此外，本发明涉及包含这种核酸分子的宿主细胞和涉及使用这种宿主细胞的重组蛋白表达的方法。

公开(公告)号：US06418176B1

公开(公告)日：2002-07-09

申请号：US09118527

申请日：1998-07-17

申请人： Steven Ho ,  Denis Foley

发明人： Steven Ho ,  Denis Foley

IPC分类号： H04L700

CPC分类号： H04L25/05 ,  H04L7/0008 ,  H04L7/005 ,  H04L7/02

摘要： A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (i) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate. The particular cycle latency may include more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate.

摘要翻译： 技术提供来自信息信号的数据。 该技术涉及与转发的时钟信号同步地在转发的时钟设备中接收信息信号。 该技术还涉及恢复与恢复时钟信号同步的包含在信息信号内的数据，使得当恢复时钟信号对于转发的时钟设备具有最佳速率时，（i）特定周期等待时间恢复数据;以及（ii） 当恢复时钟信号具有次最佳速率时，不同的周期延迟。 特定的周期延迟可以包括比不同周期等待时间更多的周期。 因此，当恢复时钟信号具有次最佳速率时，时间延迟可能更短。

公开(公告)号：US07194314B1

公开(公告)日：2007-03-20

申请号：US10641551

申请日：2003-08-15

申请人： Claus-Peter Richter ,  Steven Ho

发明人： Claus-Peter Richter ,  Steven Ho

IPC分类号： A61N1/04

CPC分类号： A61N1/0541 ,  A61N1/36036

摘要： A cochlear implant wherein the return path of the electrode array is located to increase current flow through the modiolus. The return electrode is placed at various locations outside the cochlea, and into the modiolus itself. In addition, the electrode array includes an inflatable membrane that is inflated to anchor the array in position in the cochlea with the electrode contacts pressed into contact with the modiolar wall and allowing the membrane to seal with the surrounding tissue of the cochlea, increasing the longitudinal resistance along the cochlear implant electrode, decreasing shunting of the injected current via scala tympani. In experiments that were conducted the current along the modiolus was determined to be, on average, 2.4 times larger with the return electrode in the modiolus than in an extracochlear location.

摘要翻译： 耳蜗植入物，其中电极阵列的返回路径被定位成增加流经该组织的电流。 返回电极放置在耳蜗外部的各个位置，并且进入曲柄本身。 此外，电极阵列包括充气膜，其充气以将阵列锚定在耳蜗中的适当位置，其中电极接触件与模腔壁压接并允许膜与耳蜗的周围组织密封，增加纵向 沿着耳蜗植入电极的电阻，通过鼓风鼓风降低注入电流的分流。 在进行的实验中，沿着组织的电流被确定为与组织中的返回电极相比平均高2.4倍。