公开(公告)号：US08429464B2

公开(公告)日：2013-04-23

申请号：US12617460

申请日：2009-11-12

Applicant: Ronald A. Cadima ,  Anand Singh ,  James Schaefer

Inventor： Ronald A. Cadima ,  Anand Singh ,  James Schaefer

IPC: G06F11/00

CPC classification number: G06F11/0742 ,  G06F11/073 ,  G06F12/12 ,  G07F17/32

Abstract: Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional.

公开(公告)号：US20110119474A1

公开(公告)日：2011-05-19

申请号：US12619654

申请日：2009-11-16

Applicant: Anand Singh ,  Pravinkumar Patel ,  Darren LeBlanc ,  Robert W. Crowder, JR. ,  James Schaefer ,  George Mayfield

Inventor： Anand Singh ,  Pravinkumar Patel ,  Darren LeBlanc ,  Robert W. Crowder, JR. ,  James Schaefer ,  George Mayfield

IPC: G06F15/177

CPC classification number: G06F8/65

Abstract: Various embodiments disclosed herein are directed to a serial peripheral interface-based (SPI-based) BIOS system for improved upgrading of a BIOS software image in a gaming machine. The system includes a flash BIOS chip and a SPI BIOS chip. The flash BIOS chip is operable to be written to by an Intel chipset for storage of an onboard Ethernet controller's information, wherein the flash BIOS chip may contain a new BIOS software image. The SPI BIOS chip comprises a traditional BIOS including gaming extensions to the BIOS. The SPI BIOS chip can be disabled from write actions at a jumper/circuit level. When a SPI BIOS write enable jumper circuit is ON, a write protect pin of the serial peripheral interface BIOS is in the disabled state. In this regard, when the write protect pin is in the disabled state, the SPI BIOS content may be updated to the new BIOS software image from a BIOS install compact flash. When the BIOS write enable jumper circuit is OFF, the write protect pin of the serial peripheral interface BIOS is in enabled state. In this regard, when the write protect pin is in the enabled state the serial peripheral interface BIOS content cannot be updated

Abstract translation: 本文公开的各种实施例涉及一种用于改进游戏机中的BIOS软件图像升级的基于串行外围接口（SPI）的BIOS系统。 该系统包括闪存BIOS芯片和SPI BIOS芯片。 闪存BIOS芯片可操作以由英特尔芯片组写入以存储板载以太网控制器的信息，其中闪存BIOS芯片可以包含新的BIOS软件映像。 SPI BIOS芯片包括传统的BIOS，包括BIOS的游戏扩展。 可以在跳线/电路级别对SPI BIOS芯片进行写操作。 当SPI BIOS写入使能跳线电路为ON时，串行外设接口BIOS的写保护引脚处于禁止状态。 在这方面，当写保护引脚处于禁止状态时，SPI BIOS内容可能会从BIOS安装Compact Flash更新到新的BIOS软件映像。 当BIOS写使能跳线电路为OFF时，串行外设接口BIOS的写保护引脚处于使能状态。 在这方面，当写保护引脚处于使能状态时，无法更新串行外设接口BIOS内容

公开(公告)号：US08613663B2

公开(公告)日：2013-12-24

申请号：US12619646

申请日：2009-11-16

Applicant: Nathan K. Harvey ,  Pravinkumar Patel ,  James Schaefer ,  Michael N. Dubose

Inventor： Nathan K. Harvey ,  Pravinkumar Patel ,  James Schaefer ,  Michael N. Dubose

IPC: A63F9/24 ,  A63F13/00

CPC classification number: G07F17/34 ,  G07F17/32 ,  G07F17/3202 ,  G07F17/3211

Abstract: Various embodiments are directed to gaming machines having multi-monitor support for controlling up to four monitors on a gaming device. According to one embodiment, the gaming device includes a first display for presenting a primary game. The gaming device also includes a second display and a third display where the second display is positioned above the third display. The second and third displays are used in combination to present a secondary game. The gaming device further includes a multi-core processor in communication with a first video chipset and a second video chipset, wherein the first and second video chipsets support the first, second and third monitors.

Abstract translation: 各种实施例涉及具有多监视器支持的游戏机，用于在游戏设备上控制多达四个监视器。 根据一个实施例，游戏设备包括用于呈现主游戏的第一显示器。 游戏装置还包括第二显示器和第三显示器，其中第二显示器位于第三显示器上方。 第二和第三显示器组合使用以呈现辅助游戏。 游戏装置还包括与第一视频芯片组和第二视频芯片组通信的多核处理器，其中第一和第二视频芯片组支持第一，第二和第三监视器。

公开(公告)号：US20060133945A1

公开(公告)日：2006-06-22

申请号：US11020004

申请日：2004-12-21

Applicant: Keith Reinhart ,  James Schaefer ,  Eric Cavender

Inventor： Keith Reinhart ,  James Schaefer ,  Eric Cavender

IPC: F01C1/02 ,  F04C2/00 ,  F01C1/063 ,  F04C18/00 ,  F03C2/00 ,  F03C4/00

CPC classification number: F16F15/28 ,  F01C21/003 ,  F04C18/0215 ,  F04C29/0021 ,  F16F2230/32 ,  H02K7/04 ,  Y10T29/49286

Abstract: A balancing system for different compressors utilizes a counterweight having a common exterior configuration. The mass of the counterweight is optimized for each compressor by changing the size of a recess located in the counterweight. In one embodiment, the recess is an arcuately shaped recess; and in another embodiment, the recess is a plurality of holes.

Abstract translation: 用于不同压缩机的平衡系统利用具有公共外部构造的配重。 通过改变位于配重中的凹部的尺寸，对每个压缩机优化配重的质量。 在一个实施例中，凹部是弧形凹陷; 在另一个实施例中，凹部是多个孔。

公开(公告)号：US20110117994A1

公开(公告)日：2011-05-19

申请号：US12619646

申请日：2009-11-16

Applicant: Nathan K. Harvey ,  Pravinkumar Patel ,  James Schaefer ,  Michael N. Dubose

Inventor： Nathan K. Harvey ,  Pravinkumar Patel ,  James Schaefer ,  Michael N. Dubose

IPC: A63F13/00 ,  A63F9/24

CPC classification number: G07F17/34 ,  G07F17/32 ,  G07F17/3202 ,  G07F17/3211

Abstract: Various embodiments are directed to gaming machines having multi-monitor support for controlling up to four monitors on a gaming device. According to one embodiment, the gaming device includes a first display for presenting a primary game. The gaming device also includes a second display and a third display where the second display is positioned above the third display. The second and third displays are used in combination to present a secondary game. The gaming device further includes a multi-core processor in communication with a first video chipset and a second video chipset, wherein the first and second video chipsets support the first, second and third monitors.

Abstract translation: 各种实施例涉及具有多监视器支持的游戏机，用于在游戏设备上控制多达四个监视器。 根据一个实施例，游戏设备包括用于呈现主游戏的第一显示器。 游戏装置还包括第二显示器和第三显示器，其中第二显示器位于第三显示器上方。 第二和第三显示器组合使用以呈现辅助游戏。 游戏装置还包括与第一视频芯片组和第二视频芯片组通信的多核处理器，其中第一和第二视频芯片组支持第一，第二和第三监视器。

公开(公告)号：US20050163955A1

公开(公告)日：2005-07-28

申请号：US11087279

申请日：2005-03-22

Applicant: James Schaefer ,  Marty Barris ,  Thomas Weik

Inventor： James Schaefer ,  Marty Barris ,  Thomas Weik

IPC: B01D61/14 ,  B01D39/16 ,  B01D63/06 ,  B01D63/08 ,  B01D63/14 ,  B01D69/10 ,  B01D69/12 ,  B01D71/26 ,  B01D71/30 ,  B01D71/34 ,  B01D71/42 ,  B01D71/48 ,  B01D71/50 ,  B01D71/56 ,  B01D71/68 ,  B32B5/26 ,  D04H13/00 ,  B32B3/28 ,  B29D22/00 ,  B32B27/02

CPC classification number: B01D39/1607 ,  B01D39/1623 ,  B32B5/26 ,  Y10T428/1362 ,  Y10T428/1393 ,  Y10T428/24686 ,  Y10T442/614 ,  Y10T442/62 ,  Y10T442/626 ,  Y10T442/659 ,  Y10T442/668 ,  Y10T442/671

Abstract: Improved filtration media or filter bodies can be made from fine fiber and can be formed into a filtration structure having no internal defects. The filter media or filter body comprises a collection of spot in fiber with defined fiber diameter, layer thickness and media solidity. The fine fiber is formed into a media body and obtains substantial flux and filtration efficiency. The filtration media or body can comprise single or multiple layers of fine fiber combined into the improved filter body.

Abstract translation: 改进的过滤介质或过滤体可以由细纤维制成，并且可以形成为没有内部缺陷的过滤结构。 过滤介质或过滤器主体包括具有确定的纤维直径，层厚度和介质坚固性的纤维中的斑点的集合。 细纤维形成介质体并获得显着的助焊剂和过滤效率。 过滤介质或主体可以包括单层或多层精细纤维组合成改进的过滤体。