摘要:
A complimentary switched amplifier transceiver (10) is provided which offers performance advantages and reduces system complexity over conventional half-duplex transceivers by using complimentary switched amplifiers for eliminating switches. Power output to a channel transition (31) from a transmit amplifier (26) is not degraded by a switch insertion loss in a transmit mode. Receiver noise figure is not degraded due to the switch insertion loss from the channel transition (31) to a receive amplifier (27). Switch devices and their associated control lines are eliminated, reducing circuit complexity for complimentary switched amplifier circuits such as a combined amplifier switch (12) and a first bi-directional amplifier (22).
摘要:
A high frequency transition (10) from a microstrip transmission line (57) to an MMIC coplanar waveguide (41) is provided. The microstrip transmission line (57) is representative of that typically encountered in a high frequency RF module on a first substrate (11). The MMIC coplanar waveguide (41) is representative of that encountered in low cost MMICs fabricated on a semiconductor substrate (56). An interface (15) couples the microstrip transmission line (57) to a mode converter (16). Mode converter (16) provides impedance mismatch compensation and coplanar waveguide propagation mode conditions for a connector coplanar waveguide (34) which connects from the first substrate (11) to the semiconductor substrate (56). An impedance transformer (40) provides additional impedance mismatch compensation on the semiconductor substrate (39) to complete the transition.
摘要:
A power amplifier core (40) for amplifying RF signals is provided. The power amplifier core (40) includes a first string of FET cells (46) for amplifying the RF signal. The FET cell string includes at least two FET cells (46) connected in series with an output port (48) of the amplifier core. A bias network (44) coupled between an amplifier core input port (42) and the FET cells (46) couples the RF signal to the FET cells (46). The bias network (44) includes a bias capacitor (50) and a resistor network. The bias capacitor (50) is coupled to the input port (42) for AC coupling the RF signal to an associated FET cell (46) in the FET cell string. The resistor network is coupled from the bias capacitor (50) to the associated FET cell (46) for providing a DC bias to the associated FET cell (46).
摘要:
A differential pair, push-push oscillator for generating clocking signals. This oscillator consists of two, single transistor oscillators that both oscillate at f.sub.o with a 180.degree. phase difference. The phase difference is caused by the direct connection of the transistors' drains. A current source, connected to the transistors' drains, biases the transistors. The common drain connection also serves as an output for the differential pair, push-push oscillator. This output, a stable, relatively high power signal of frequency 2f.sub.o, is a composite of the two signals from the single transistor oscillators.