Method for manufacturing a semiconductor component contactable on both
sides
    3.
    发明授权
    Method for manufacturing a semiconductor component contactable on both sides 失效
    用于制造在两侧可接触的半导体组件的方法

    公开(公告)号:US4959328A

    公开(公告)日:1990-09-25

    申请号:US199922

    申请日:1988-05-27

    摘要: A method for manufacturing semiconductor components contactable on both sides, in particular IMPATT diodes. The active silicon layers of the IMPATT diode are grown onto a silicon substrate. The first silicon layer grown onto the silicon substrate has a high boron/germanium doping level and acts as an etch atop layer when the substrate is removed. The boron/germanium doping of the first silicon layer compensates for the mechanical stress in the silicon layer generated by the boron doping.

    摘要翻译: 一种用于制造在两侧可接触的半导体组件的方法,特别是IMPATT二极管。 IMPATT二极管的活性硅层生长在硅衬底上。 在硅衬底上生长的第一硅层具有高硼/锗掺杂水平,并且当去除衬底时用作顶层的蚀刻。 第一硅层的硼/锗掺杂补偿由硼掺杂产生的硅层中的机械应力。

    Semiconductor devices with CSP packages and method for making them
    4.
    发明授权
    Semiconductor devices with CSP packages and method for making them 失效
    具有CSP封装的半导体器件及其制造方法

    公开(公告)号:US6020217A

    公开(公告)日:2000-02-01

    申请号:US26693

    申请日:1998-02-20

    IPC分类号: H01L21/60 H01L21/44

    摘要: The invention relates to a semiconductor device which includes a packaged electrical component such as an IC chip, wherein terminal posts are realized within the chip area without additional wafer surface being required beyond the chip edge. A direct feedthrough of the individual electrical connections by way of downwardly extending terminal posts that are connected to bonding pads at the top of the chip results in a small lead length and thus lesser parasitic influences, which in turn results in optimum conditions for use at super-high frequencies. Furthermore, a process for making the semiconductor device offers the option of forming deep vertical trenches on the chip edge and to thus implement separation etching for dicing. During this process, the coverage of the side surface with encapsulating material effects a passivation on the chip edge without further outlay. Expensive rewiring of the connections on the bottom side of the chip is not necessarily due to the terminal posts.

    摘要翻译: 本发明涉及一种半导体器件,其包括诸如IC芯片的封装电子部件,其中端子柱被实现在芯片区域内,而没有在芯片边缘之外需要额外的晶片表面。 通过向下延伸的连接到芯片顶部的接合焊盘的端子柱的各个电连接件的直接馈通导致小的引线长度,从而导致较小的寄生影响,这又导致在超级 高频率 此外,用于制造半导体器件的工艺提供了在芯片边缘上形成深垂直沟槽并因此实现用于切割的分离蚀刻的选择。 在此过程中,具有封装材料的侧表面覆盖在芯片边缘上实现钝化,而无需进一步的支出。 在芯片底部的连接的昂贵的重新布线不一定是由于端子柱。

    Mask for X-ray lithography
    5.
    发明授权
    Mask for X-ray lithography 失效
    X光光刻面具

    公开(公告)号:US4647517A

    公开(公告)日:1987-03-03

    申请号:US751842

    申请日:1985-07-03

    CPC分类号: G03F1/22 H01L21/30608

    摘要: The invention relates to a mask for X-ray lithography, in particular, for the manufacture of VLSI semiconductor components, which is economical and reliable in its manufacture. The mask should transfer absorber structures down to the submicron range. Lateral mechanical distortions are avoided by a tension-compensated carrier membrane of simultaneously B and Ge doped silicon. This carrier membrane is also optically more transparent than known Si membranes doped only with B, which facilitates optical alignment of the mask.

    摘要翻译: 本发明涉及一种用于X射线光刻的掩模,特别是用于制造VLSI半导体元件,其在其制造中是经济可靠的。 掩模应将吸收体结构转移到亚微米范围内。 通过同时B和Ge掺杂硅的张力补偿载体膜避免横向机械扭曲。 该载体膜也比仅用B掺杂的已知Si膜更透明,这有利于掩模的光学对准。

    Semiconductor body with heat sink
    6.
    发明授权
    Semiconductor body with heat sink 失效
    半导体体散热片

    公开(公告)号:US4910583A

    公开(公告)日:1990-03-20

    申请号:US201734

    申请日:1988-06-02

    摘要: The invention relates to a semiconductor body, which is composed of at least one semiconductor device, especially one impatt-diode, with integrated heat sink. The series of semiconductor layers, out of which the semiconductor device is produced, is made up of one first p.sup.+ -doped semiconductor layer, which has the function of an etching stop layer, of a contact layer and a buffer layer at the same time.

    摘要翻译: 本发明涉及半导体本体,其由至少一个具有集成散热器的半导体器件,特别是一个二极管形成。 制造半导体器件的半导体层系列由同时具有接触层和缓冲层的具有蚀刻停止层功能的一个第一p +掺杂半导体层构成。