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公开(公告)号：US4241425A
公开(公告)日：1980-12-23
申请号：US10839
申请日：1979-02-09
IPC分类号： G11C11/34 , G11C11/406 , G11C11/4063 , G11C11/408 , G11C11/40
CPC分类号： G11C11/408 , G11C11/406 , G11C11/4063
摘要： An MOS dynamic random access memory (RAM) includes an array of memory cells arranged in rows and columns. The array is divided into two or more sub-arrays. In an operating cycle where a cell is being accessed for reading and/or writing, only the sub-array containing the accessed cell is fully selected while the other sub-arrays are partially selected. A fully selected sub-array is one in which both a row and a column are selected, whereas in a partially selected sub-array, only a row is selected. In the partially selected sub-array where only refreshing of the cells in the selected row takes place, the column decoders and drivers remain inactive throughout the memory cycle.
摘要翻译： MOS动态随机存取存储器（RAM）包括以行和列排列的存储器单元阵列。 阵列分为两个或更多个子阵列。 在读取和/或写入单元格的操作周期中，只有包含被访问单元格的子阵列被完全选择，而其他子阵列被部分选择。 完全选择的子数组是选择行和列的子数组，而在部分选择的子数组中，只选择一行。 在部分选择的子阵列中，只有刷新所选行中的单元格，列解码器和驱动器在整个存储器周期中保持不活动。
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公开(公告)号：US4228528A
公开(公告)日：1980-10-14
申请号：US10739
申请日：1979-02-09
申请人： Ronald P. Cenker , Frank J. Procyk
发明人： Ronald P. Cenker , Frank J. Procyk
CPC分类号： G11C29/781
摘要： A memory is provided with standard rows and columns and spare rows and columns for substitution for standard rows and columns found to have defective cells. Each of the decoders associated with a standard row and/or column includes provision for being disconnected if found to be associated with a defective row or column. Each of the decoders associated with a spare row and/or column is designed normally to be deselected for any address but to be able to assume the address of any disconnected row or column. Disconnection of the standard decoders and substitution of the spare decoders are made possible by appropriate inclusion of fusible links which can be selectively opened by laser irradiation.
摘要翻译： 为内存提供标准行和列以及备用行和列，用于替代发现有缺陷单元格的标准行和列。 与标准行和/或列相关联的每个解码器包括如果发现与有缺陷的行或列相关联的断开的设置。 与备用行和/或列相关联的每个解码器被设计为通常被取消选择用于任何地址，但是能够承担任何断开的行或列的地址。 标准解码器的断开和备用解码器的替代可以通过适当地包括可以通过激光照射选择性地打开的可熔链路成为可能。
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公开(公告)号：US4183096A
公开(公告)日：1980-01-08
申请号：US909367
申请日：1978-05-25
IPC分类号： G06F12/16 , G06F11/10 , G11C11/401 , G11C29/00 , G11C29/04 , G11C29/42 , G11C29/44 , G11C13/00
CPC分类号： G06F11/106 , G11C29/04 , G11C29/42 , G11C29/44
摘要： The storage space of the instant system is considered, for refresh purposes, to contain 512 groups of 26 bit digital words with each group containing 128 such words. Memory refresh is implemented by sequentially refreshing the groups of digital words at the rate of one group every 2.8 microseconds, giving an expected total memory refresh time of approximately 1.43 milliseconds. A particular digital word from each group of digital words refreshed is read from the memory and transmitted to a parity check circuit which generates fault signals for any digital word having faulty parity. At the end of each of the approximately 1.43 millisecond refresh cycles, the particular word read from each group refreshed is changed so that at the end of 128 full refresh cycles (approximately 184 milliseconds), the parity of every digital word in the memory has been checked. Further, circuitry is provided to store the location of the first failing digital word in a trap register in response to an indication of faulty parity.
摘要翻译： 考虑到即时系统的存储空间，为了刷新目的，包含512组26位数字字，每组包含128个这样的字。 通过以每2.8微秒一组的速率顺序刷新数字字组来实现存储器刷新，从而给出大约1.43毫秒的预期总存储器刷新时间。 刷新的每组数字字的特定数字字从存储器中读出并发送到奇偶校验电路，该校验电路为任何具有故障奇偶校验的数字字产生故障信号。 在大约1.43毫秒刷新周期结束时，刷新的每个组读取的特定字被改变，使得在128个完全刷新周期（约184毫秒）结束时，存储器中每个数字字的奇偶校验已经被 检查。 此外，提供电路以响应于错误奇偶校验的指示将第一故障数字字的位置存储在陷阱寄存器中。
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