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1.发明授权Apparatus and method for suspending and resuming software applications on a computer 失效用于在计算机上挂起和恢复软件应用程序的装置和方法
公开(公告)号：US4907150A
公开(公告)日：1990-03-06
申请号：US225570
申请日：1988-07-26
申请人： Ronald X. Arroyo , Michael N. Day , Jimmie D. Edrington , James T. Hanna , Gary T. Hunt , Steven T. Pancoast
发明人： Ronald X. Arroyo , Michael N. Day , Jimmie D. Edrington , James T. Hanna , Gary T. Hunt , Steven T. Pancoast
CPC分类号： G06F1/3246 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F9/461 , G05B2219/34306 , G05B2219/34365 , G06F11/14 , Y02P70/163 , Y02P70/169
摘要： A method and apparatus for powering down a computer system while saving the state of the system at power down is disclosed. The system maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at that same point at a later time. The time at which the system may be powered down and then powered back up again is totally arbitrary and depends only upon the user of the system. At the time the system is powered off, the contents of all active registers as well as the states of all I/O devices in the system are stored in a special save area of system memory. This special save area is provided with power during the suspended time in order to retain the state of the system at the time it was powered down. By using this special save suspend area, the main memory area of the system is available to any application programs independently of the system save memory requirements. Additionally, the system may be powered on and off under software control thereby providing the capability for unattended system operation using an alarm function.
摘要翻译： 公开了一种在断电的同时节省系统状态的电源系统的方法和装置。 该系统保持在任何时候暂停在系统上运行的应用程序的执行的能力，并在稍后的时间恢复该同一点处的应用程序的执行。 系统可以关闭电源，然后重新上电的时间完全是任意的，并且仅取决于系统的用户。 当系统断电时，所有活动寄存器的内容以及系统中所有I / O设备的状态都存储在系统内存的特殊保存区域中。 这个特殊的保存区域在暂停时间内提供电源，以便在断电时保持系统的状态。 通过使用这个特殊的保存挂起区域，系统的主存储区域可用于任何应用程序，独立于系统节省存储器要求。 此外，系统可以在软件控制下通电和关断，从而提供使用报警功能进行无人值守系统操作的能力。
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2.发明授权Method for communicating instructions and data between a processor and external devices 失效在处理器和外部设备之间传送指令和数据的方法公开(公告)号：US07778271B2
公开(公告)日：2010-08-17
申请号：US11207970
申请日：2005-08-19
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的方法。 该方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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公开(公告)号：US4538265A
公开(公告)日：1985-08-27
申请号：US478574
申请日：1983-03-24
申请人： Michael N. Day , Claude D. Miller
发明人： Michael N. Day , Claude D. Miller
CPC分类号： G06F11/141
摘要： A method and apparatus for instruction parity error recovery in a programmable data processor wherein the instruction parity error is logged for future reference, the instruction causing the error is reloaded to memory and the program is restarted at the point of error. This method for "soft" recovery from an instruction parity error forces a No-Operation instruction onto the processor's instruction bus in place of the faulty instruction when a parity error is detected during instruction fetch, stores the address of the instruction having the parity error, and forces the next instruction to the processor from a parity error recovery routine. The parity error recovery routine logs the error, restores the instruction from local disk storage or from a remote host system in communication with the programmable data processor and forces the processor to resume fetching instructions at the address where the error occurred.
摘要翻译： 一种可编程数据处理器中用于指令奇偶校验错误恢复的方法和装置，其中指令奇偶校验错误被记录以供将来参考，引起错误的指令被重新加载到存储器，并且程序在错误点被重新启动。 这种从指令奇偶校验错误中恢复的“软”方法在指令获取期间检测到奇偶校验错误时，将无操作指令强制到处理器的指令总线上代替有故障的指令，存储具有奇偶校验错误的指令的地址， 并从奇偶校验错误恢复程序强制下一条指令给处理器。 奇偶校验错误恢复例程记录错误，恢复来自本地磁盘存储器的指令或与可编程数据处理器通信的远程主机系统，并强制处理器在发生错误的地址恢复获取指令。
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公开(公告)号：US20090217300A1
公开(公告)日：2009-08-27
申请号：US12361907
申请日：2009-01-29
CPC分类号： G06F13/24
摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于与处理器事件设施进行通信的系统和方法。 系统和方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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公开(公告)号：US20090204781A1
公开(公告)日：2009-08-13
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译： 提供了用于限制处理器的本地存储器的大小的系统。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。 当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。
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公开(公告)号：US07533238B2
公开(公告)日：2009-05-12
申请号：US11208376
申请日：2005-08-19
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译： 提供了一种用于限制处理器的本地存储器的大小的方法。 与用于设置本地存储大小限制的处理器相关联地提供设施。 该设施是一个特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化上下文切换时，操作系统设置存储在本地存储限制寄存器中的值 在处理器中。 当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为 用于访问本地存储。
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7.发明申请System and Method for Providing a Mediated External Exception Extension for a Microprocessor 审中-公开为微处理器提供介入的外部异常扩展的系统和方法公开(公告)号：US20080034193A1
公开(公告)日：2008-02-07
申请号：US11462601
申请日：2006-08-04
IPC分类号： G06F7/38
CPC分类号： G06F13/24 , G06F9/32 , G06F9/4812 , G06F2209/481
摘要： A system and method for providing a mediated external exception extension for a microprocessor are provided. With the system and method, in response to an external exception, a hypervisor determines if the associated external interrupt is directed to a logical partition (LPAR) that has external interrupt handling enabled. If so, the hypervisor sets appropriate state restore registers (SRRs) and passes control to an external interrupt handler of the LPAR. If external interrupt handling is not currently enabled by the LPAR, the hypervisor sets a mediated exception request and returns control to the LPAR. Once the operating system of the logical partition re-enables external interrupt handling, a mediated external interrupt occurs, state information for the LPAR is set in the SRRs, and the external interrupt handler of the LPAR is invoked. In this way, external interrupts may be received by the hypervisor even when external interrupt handling is disabled.
摘要翻译： 提供了一种用于为微处理器提供介导的外部异常扩展的系统和方法。 利用系统和方法，响应于外部异常，管理程序确定相关联的外部中断是否被引导到启用了外部中断处理的逻辑分区（LPAR）。 如果是这样，管理程序设置适当的状态恢复寄存器（SRR），并将控制权传递给LPAR的外部中断处理程序。 如果LPAR当前未启用外部中断处理，管理程序将设置介入的异常请求并将控制权返回给LPAR。 一旦逻辑分区的操作系统重新启用外部中断处理，就会发生中介的外部中断，LPAR的状态信息设置在SRR中，并且调用LPAR的外部中断处理程序。 以这种方式，即使禁用外部中断处理，管理程序也可以接收外部中断。
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公开(公告)号：US07930457B2
公开(公告)日：2011-04-19
申请号：US12361907
申请日：2009-01-29
CPC分类号： G06F13/24
摘要： Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了与处理器事件设施通信的机制。 这些机制使用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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9.发明授权公开(公告)号：US07869459B2
公开(公告)日：2011-01-11
申请号：US12129114
申请日：2008-05-29
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的机制。 该机制利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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10.发明申请SYSTEM AND METHOD FOR HANDLING MULTIPLE ALIASED SHADOW REGISTER NUMBERS TO ENHANCE LOCK ACQUISITION 审中-公开用于处理多个被遮挡的阴影寄存器编号的系统和方法以增加锁定采集公开(公告)号：US20080162823A1
公开(公告)日：2008-07-03
申请号：US11619033
申请日：2007-01-02
申请人： Michael N. Day , Charles R. Johns , Roy M. Kim , Peichun P. Liu
发明人： Michael N. Day , Charles R. Johns , Roy M. Kim , Peichun P. Liu
CPC分类号： G06F9/30087 , G06F9/30116 , G06F12/0815 , Y02D10/13
摘要： Exemplary embodiments include a method for enhancing lock acquisition in a multiprocessor system, the method including: sending a lock-load instruction from a first processor to a cache; setting a reservation flag for the first processor, storing a reservation address, storing a shadow register number, and sending lock data to the first processor in response to the lock-load instruction; placing the lock data in target and shadow registers of the first processor; determining from the lock data whether lock is taken; resending the lock-load instruction from the first processor to the cache upon a determination that the lock is taken; determining whether the reservation flag is still set and its main memory address and shadow register number match with the saved reservation address and shadow register number for the first processor; sending a status-quo signal to the first processor without resending the lock data to the first processor upon a determination that the reservation flag is still set for the first processor; and copying the lock data from the associated shadow register to the target register in response to the status-quo signal.
摘要翻译： 示例性实施例包括用于增强多处理器系统中的锁获取的方法，所述方法包括：将锁定加载指令从第一处理器发送到高速缓存; 设置第一处理器的预约标志，存储预约地址，存储影子寄存器号码，以及响应于锁定加载指令向第一处理器发送锁定数据; 将锁定数据放置在第一处理器的目标和影子寄存器中; 从锁定数据确定是否采取锁定; 在确定锁定时，将锁定加载指令从第一处理器重新发送到高速缓存; 确定保留标志是否仍然设置，并且其主存储器地址和影子寄存器号码与第一处理器的保存的预留地址和影子寄存器号码相匹配; 在确定所述预留标志仍然被设置用于所述第一处理器时，向所述第一处理器发送状态信号而不将所述锁定数据重新发送到所述第一处理器; 并且响应于状态信号将锁定数据从相关联的影子寄存器复制到目标寄存器。
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