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公开(公告)号：US5612547A
公开(公告)日：1997-03-18
申请号：US462405
申请日：1995-06-05
IPC分类号： H01L29/24 , H01L29/772 , H01L29/808 , H01L29/812 , H01L31/0312 , H01L27/095 , H01L29/80 , H01L31/112
CPC分类号： H01L29/1608 , H01L29/7722 , H01L29/8083 , H01L29/8122
摘要： A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.
摘要翻译： 尽管可以使用任何碳化硅多型体，但由碳化硅制成的静电感应晶体管，优选为6H型。 优选的静态感应晶体管是凹入的肖特基势垒栅型。 因此，提供了碳化硅衬底。 然后，在基板上设置碳化硅漂移层，其中漂移层具有远离衬底延伸的两个间隔开的突起或指状物。 漂移层的每个突起具有设置在其上的碳化硅源区域。 然后沿两个突起之间的漂移层提供栅极材料。 在栅极材料上提供导电栅极触点，并且在每个源极区域上提供导电源极触点。 沿着衬底提供导电漏极接触。 考虑静态感应晶体管的其他栅极类型。 例如，可以采用平面肖特基势垒栅极。 此外，可以使用凹入或平面的MOS栅极，如PN结栅极。
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公开(公告)号：US5945701A
公开(公告)日：1999-08-31
申请号：US995080
申请日：1997-12-19
IPC分类号： H01L29/80 , H01L29/12 , H01L29/772 , H01L29/78 , H01L29/808 , H01L29/812
CPC分类号： H01L29/7722
摘要： A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.
摘要翻译： 具有源极，漏极和栅极区域的静态感应晶体管。 沟道区域被定义在相邻栅极之间，并且从沟道区域的端部到漏极限定漂移区域。 通道和漂移区具有预定的掺杂浓度，其中沟道区的掺杂浓度大于漂移区的掺杂浓度。
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公开(公告)号：US5903020A
公开(公告)日：1999-05-11
申请号：US877847
申请日：1997-06-18
IPC分类号： H01L21/04 , H01L29/06 , H01L29/24 , H01L29/772 , H01L29/80
CPC分类号： H01L29/7722 , H01L29/66068 , H01L29/0619 , H01L29/0696 , H01L29/1608 , H01L29/32
摘要： A static induction transistor having a silicon carbide substrate upon which is deposited a silicon carbide layer arrangement. The layer arrangement has a plurality of spaced gate regions for controlling current flow from a source region to a drain region vertically spaced from the source region by a drift layer. The pitch distance p between gate regions is 1 to 5 microns and the drift layer thickness d is also 1 to 5 microns.In one embodiment the source regions are positioned alternatively with the gate regions and are formed in a top layer of high doping concentration. In another embodiment the gate regions are ion implanted in the layer arrangement.In another embodiment the structure includes a dual oxide layer covering gate and source or drain regions, and in yet another embodiment contacts for the drain, source and gate regions are located on the same side of the substrate member.
摘要翻译： 一种具有碳化硅衬底的静电感应晶体管，沉积碳化硅层布置。 层布置具有多个间隔开的栅极区域，用于控制从源极区域到通过漂移层与源极区域垂直间隔开的漏极区域的电流。 栅区之间的间距距离p为1至5微米，漂移层厚度d也为1至5微米。 在一个实施例中，源极区域与栅极区域交替定位并且形成在高掺杂浓度的顶层中。 在另一个实施例中，栅极区域被离子注入层布置。 在另一个实施例中，该结构包括覆盖栅极和源极或漏极区域的双重氧化物层，并且在又一实施例中，用于漏极，源极和栅极区域的触点位于衬底构件的相同侧上。
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公开(公告)号：US5705830A
公开(公告)日：1998-01-06
申请号：US708447
申请日：1996-09-05
IPC分类号： H01L21/04 , H01L29/772 , H01L31/0312
CPC分类号： H01L29/66068 , H01L29/7722
摘要： A static induction transistor includes a substrate and a drift layer with different doping levels. At least two mesas are formed on the drift layer and a heavily doped region is positioned on a top surface of each of the mesas. A gate contact extends along a bottom of a recess between the mesas and along a side of each of the mesas forming the recess. The gate contact also extends along a portion of the top surface of each of the mesas. In one embodiment of the invention, a notch is formed in the top surface of the mesas between the gate contact and the heavily doped region.
摘要翻译： 静电感应晶体管包括衬底和具有不同掺杂水平的漂移层。 在漂移层上形成至少两个台面，并且重掺杂区域位于每个台面的顶表面上。 栅极接触沿着台面之间的凹部的底部并沿着形成凹部的每个台座的一侧延伸。 栅极接触还沿着每个台面的顶表面的一部分延伸。 在本发明的一个实施例中，在栅极接触和重掺杂区域之间的台面的顶表面中形成有凹口。
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5.发明授权Self-aligned gate fabrication process for silicon carbide static induction transistors 失效碳化硅静电感应晶体管的自对准栅极制造工艺
公开(公告)号：US5807773A
公开(公告)日：1998-09-15
申请号：US688587
申请日：1996-07-30
IPC分类号： H01L21/04 , H01L21/337
CPC分类号： H01L29/66068 , Y10S438/931
摘要： A method of aligning a gate and a source of a silicon carbide static induction transistor comprising the steps of depositing an oxide layer over the transistor, forming oxide spacers from the oxide layer where the oxide spacers are adjacent the source, depositing a metal layer over the transistor and removing the oxide spacers so that the resulting gates are accurately aligned with the source.
摘要翻译： 一种对准碳化硅静电感应晶体管的栅极和源极的方法，包括以下步骤：在所述晶体管上沉积氧化物层，从所述氧化物层形成氧化物间隔物，其中所述氧化物间隔物邻近所述源，在所述氧化物层上沉积金属层 去除氧化物间隔物，使得所得到的栅极与源极准确对准。
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6.发明授权
公开(公告)号：US5510630A
公开(公告)日：1996-04-23
申请号：US138908
申请日：1993-10-18
IPC分类号： H01L21/82 , H01L27/115 , H01L29/24 , H01L29/423 , H01L29/78 , H01L29/04 , H01L29/48
CPC分类号： H01L29/1608 , H01L21/8213 , H01L27/115 , H01L29/7838
摘要： A non-volatile random access memory (NVRAM) cell that utilizes a simple, single-transistor DRAM cell configuration. The present NVRAM employs an enhancement mode nMOS transistor made as an accumulation mode transistor. The transistor has an n-type silicon carbide channel layer on a p-type silicon carbide buffer layer, with the channel and buffer layers being on a highly resistive silicon carbide substrate. The transistor also has n+ source and drain contact regions on the channel layer. A polysilicon/oxide/metal capacitor is preferably used which has a very low leakage current. Furthermore, this type of capacitor can be stacked on top of the transistor to save area and achieve high cell density. It is preferred to use a non-reentrant (edgeless) gate transistor structure to further reduce edge effects.
摘要翻译： 利用简单的单晶体管DRAM单元配置的非易失性随机存取存储器（NVRAM）单元。 目前的NVRAM采用了作为累积模式晶体管制成的增强型nMOS晶体管。 晶体管在p型碳化硅缓冲层上具有n型碳化硅沟道层，其中沟道和缓冲层位于高电阻碳化硅衬底上。 晶体管还在沟道层上具有n +源极和漏极接触区域。 优选使用具有非常低的漏电流的多晶硅/氧化物/金属电容器。 此外，这种类型的电容器可以堆叠在晶体管的顶部以节省面积并实现高电池密度。 优选使用不可重入（无边缘）栅极晶体管结构来进一步减少边缘效应。
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