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39 条记录 (耗时 0.022 秒)

    Silicon carbide static induction transistor
    1.
    发明授权
    Silicon carbide static induction transistor 失效
    碳化硅静电感应晶体管

    公开(公告)号：US5612547A

    公开(公告)日：1997-03-18

    申请号：US462405

    申请日：1995-06-05

    申请人： Rowland C. Clarke ,  Richard R. Siergiej ,  Saptharishi Sriram

    发明人： Rowland C. Clarke ,  Richard R. Siergiej ,  Saptharishi Sriram

    IPC分类号： H01L29/24 ,  H01L29/772 ,  H01L29/808 ,  H01L29/812 ,  H01L31/0312 ,  H01L27/095 ,  H01L29/80 ,  H01L31/112

    CPC分类号： H01L29/1608 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/8122

    摘要： A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed. Furthermore, recessed or planar MOS gates may be utilized, as may a PN junction gate.

    摘要翻译： 尽管可以使用任何碳化硅多型体，但由碳化硅制成的静电感应晶体管，优选为6H型。 优选的静态感应晶体管是凹入的肖特基势垒栅型。 因此，提供了碳化硅衬底。 然后，在基板上设置碳化硅漂移层，其中漂移层具有远离衬底延伸的两个间隔开的突起或指状物。 漂移层的每个突起具有设置在其上的碳化硅源区域。 然后沿两个突起之间的漂移层提供栅极材料。 在栅极材料上提供导电栅极触点，并且在每个源极区域上提供导电源极触点。 沿着衬底提供导电漏极接触。 考虑静态感应晶体管的其他栅极类型。 例如，可以采用平面肖特基势垒栅极。 此外，可以使用凹入或平面的MOS栅极，如PN结栅极。

    Silicon carbide power MESFET with surface effect supressive layer
    2.
    发明授权
    Silicon carbide power MESFET with surface effect supressive layer 失效
    碳化硅功率MESFET具有表面效应抑制层

    公开(公告)号：US5925895A

    公开(公告)日：1999-07-20

    申请号：US812227

    申请日：1997-03-06

    申请人： Saptharishi Sriram ,  Rowland C. Clarke

    发明人： Saptharishi Sriram ,  Rowland C. Clarke

    IPC分类号： H01L21/04 ,  H01L29/24 ,  H01L29/812 ,  H01L31/0312 ,  H01L29/12

    CPC分类号： H01L29/1608 ,  H01L21/045 ,  H01L29/66068 ,  H01L29/8128

    摘要： A silicon carbide metal semiconductor field effect transitor fabricated on silicon carbide substrate with a layer which suppresses surface effects, and method for producing same. The surface-effect-suppressive layer may be formed on exposed portions of the transistor channel and at least a portion of each contact degenerate region. The surface-effect-suppressive layer may be made of undoped silicon carbide or of an insulator, such as silicon dioxide or silicon nitride. If the surface-effect-suppressive layer is made of silicon dioxide, it is preferred that the layer be fabricated of a combination of thermally-grown and chemical vapor deposition deposited silicon dioxide.

    摘要翻译： 在具有抑制表面效应的层的碳化硅衬底上制造的碳化硅金属半导体场效应晶体管及其制造方法。 表面效应抑制层可以形成在晶体管沟道的暴露部分和每个接触退化区域的至少一部分上。 表面效应抑制层可以由未掺杂的碳化硅或诸如二氧化硅或氮化硅的绝缘体制成。 如果表面效应抑制层由二氧化硅制成，则优选由热生长和化学气相沉积沉积的二氧化硅的组合制成该层。

    Methods of fabricating transistors having buried P-type layers coupled to the gate
    3.
    发明授权
    Methods of fabricating transistors having buried P-type layers coupled to the gate 有权
    制造具有连接到栅极的P型层的晶体管的方法

    公开(公告)号：US07943972B2

    公开(公告)日：2011-05-17

    申请号：US12627743

    申请日：2009-11-30

    申请人： Saptharishi Sriram ,  Matt Willis

    发明人： Saptharishi Sriram ,  Matt Willis

    IPC分类号： H01L29/812 ,  H01L21/338

    CPC分类号： H01L29/8128 ,  H01L29/1029 ,  H01L29/1066 ,  H01L29/808

    摘要： A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

    摘要翻译： 提供了一种金属半导体场效应晶体管（MESFET）的晶胞。 MESFET具有源极，漏极和栅极。 栅极在源极和漏极之间以及n型导电沟道层之间。 在源极和漏极之间的栅极下方提供p型导电区域。 p型导电区域与n型导电沟道层间隔开并电耦合到栅极。 本文还提供了相关方法。

    Diode Having Reduced On-resistance and Associated Method of Manufacture
    5.
    发明申请
    Diode Having Reduced On-resistance and Associated Method of Manufacture 有权
    二极管具有降低的导通电阻和相关的制造方法

    公开(公告)号：US20080197360A1

    公开(公告)日：2008-08-21

    申请号：US11675658

    申请日：2007-02-16

    申请人： Saptharishi Sriram ,  Thomas J. Smith ,  Helmut Hagleitner

    发明人： Saptharishi Sriram ,  Thomas J. Smith ,  Helmut Hagleitner

    IPC分类号： H01L29/868 ,  H01L21/329 ,  H01L29/24

    CPC分类号： H01L29/1608 ,  H01L23/291 ,  H01L23/31 ,  H01L29/0657 ,  H01L29/6606 ,  H01L29/6609 ,  H01L29/861 ,  H01L29/868 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A diode structure having a reduced on-resistance in the forward-biased condition includes semiconductor layers, preferably of silicon carbide. The anode and cathode of the device are located on the same side of the bottom semiconductor layer, providing lateral conduction across the diode body. The anode is positioned on a semiconductor mesa, and the sides of the mesa are covered with a nonconductive spacer extending from the anode to the bottom layer. An ohmic contact, preferably a metal silicide, covers the surface of the bottom layer between the spacer material and the cathode. The conductive path extends from anode to cathode through the body of the mesa and across the bottom semiconductor layer, including the ohmic contact. The method of forming the diode includes reacting layers of silicon and metal on the appropriate regions of the diode to form an ohmic contact of metal silicide.

    摘要翻译： 在正向偏置状态下具有降低的导通电阻的二极管结构包括优选为碳化硅的半导体层。 器件的阳极和阴极位于底部半导体层的同一侧，提供横跨二极管体的横向导通。 阳极定位在半导体台面上，并且台面的侧面被从阳极延伸到底层的非导电间隔物覆盖。 欧姆接触，优选金属硅化物，覆盖在间隔物材料和阴极之间的底层的表面。 导电路径从阳极延伸穿过台面的主体并穿过底部半导体层，包括欧姆接触。 形成二极管的方法包括在二极管的适当区域上反应硅和金属层以形成金属硅化物的欧姆接触。

    Power FETS with improved high voltage performance
    7.
    发明授权
    Power FETS with improved high voltage performance 失效
    功率FETS具有改进的高电压性能

    公开(公告)号：US5043777A

    公开(公告)日：1991-08-27

    申请号：US593371

    申请日：1990-09-28

    申请人： Saptharishi Sriram

    发明人： Saptharishi Sriram

    IPC分类号： H01L29/778 ,  H01L29/80

    CPC分类号： H01L29/7787 ,  H01L29/802

    摘要： An undoped surface layer over and lattice matched to the n-channel layer between the gate contact and the spaced apart source and drain n+ regions in power FETs made of group III-V compounds minimizes surface effects that preclude such devices from operating efficiently at high voltages, and improves reliability. The undoped surface layer may be grown on the n-channel layer before the layer forming the n+ regions, or where the n+ regions can be formed in the undoped surface layer. The invention is especially suitable for GaAs MESFETs and HEMTs.

    摘要翻译： 在III-V族化合物制成的功率FET中栅极接触和间隔开的源极和漏极n +区之间的n沟道层上的未掺杂的表面层使表面效应最小化，从而使得这些器件不能在高电压下有效地工作 ，并提高可靠性。 在形成n +区的层之前，或者可以在未掺杂的表面层中形成n +区的情况下，可以在n沟道层上生长未掺杂的表面层。 本发明特别适用于GaAs MESFET和HEMT。

    SCHOTTKY CONTACT
    8.
    发明申请
    SCHOTTKY CONTACT 有权
    肖特友联系人

    公开(公告)号：US20130234278A1

    公开(公告)日：2013-09-12

    申请号：US13414286

    申请日：2012-03-07

    申请人： Helmut Hagleitner ,  Saptharishi Sriram

    发明人： Helmut Hagleitner ,  Saptharishi Sriram

    IPC分类号： H01L29/47 ,  H01L21/28

    CPC分类号： H01L29/475 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/452 ,  H01L29/7786 ,  H01L29/872

    摘要： The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.

    摘要翻译： 本公开涉及半导体器件的肖特基接触。 半导体器件具有由位于衬底上的一个或多个外延层形成的主体。 肖特基接触可以包括肖特基层，第一扩散阻挡层和第三层。 肖特基层由第一金属形成并且设置在主体的第一表面的至少一部分上。 第一扩散阻挡层由第一金属的硅化物形成，并且设置在肖特基层上。 第三层由第二金属形成，并且设置在第一扩散阻挡层上。 在一个实施例中，第一金属是镍，因此硅化物是硅化镍。 可以在肖特基层，第一扩散阻挡层和第三层之间或之上提供各种其它层。

    Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods
    10.
    发明授权
    Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods 有权
    金属半导体场效应晶体管（MESFETS）具有不同厚度的沟道和相关方法

    公开(公告)号：US07402844B2

    公开(公告)日：2008-07-22

    申请号：US11289158

    申请日：2005-11-29

    申请人： Saptharishi Sriram

    发明人： Saptharishi Sriram

    IPC分类号： H01L29/778

    CPC分类号： H01L29/1029 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/812

    摘要： A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The unit cell includes a MESFET having a source, a drain and a gate. The gate is between the source and the drain and on a channel layer of the MESFET. The channel layer has a first thickness on a source side of the channel layer and a second thickness, thicker than the first thickness, on a drain side of the channel layer. Related methods of fabricating MESFETs are also provided herein.

    摘要翻译： 提供了一种金属半导体场效应晶体管（MESFET）的晶胞。 该单元包括具有源极，漏极和栅极的MESFET。 栅极位于源极和漏极之间以及MESFET的沟道层上。 沟道层在沟道层的漏极侧具有在沟道层的源极侧的第一厚度和比第一厚度更厚的第二厚度。 本文还提供了制造MESFET的相关方法。