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1.发明授权Passive element memory array incorporating reversible polarity word line and bit line decoders 有权无源元件存储阵列，包含可逆极性字线和位线解码器公开(公告)号：US07554832B2
公开(公告)日：2009-06-30
申请号：US11461339
申请日：2006-07-31
IPC分类号： G11C11/00
CPC分类号： G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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2.发明申请PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 有权被动元素存储阵列引入可反转的极性字线和位线解码器公开(公告)号：US20080025066A1
公开(公告)日：2008-01-31
申请号：US11461339
申请日：2006-07-31
IPC分类号： G11C11/00
CPC分类号： G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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3.发明授权Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders 有权使用包含可逆极性字线和位线解码器的无源元件存储器阵列的方法公开(公告)号：US07463546B2
公开(公告)日：2008-12-09
申请号：US11461364
申请日：2006-07-31
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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公开(公告)号：US20080025134A1
公开(公告)日：2008-01-31
申请号：US11461372
申请日：2006-07-31
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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5.发明申请METHOD FOR USING A PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 有权使用无源元件存储器阵列的方法，包含可反映的极性字线和位线解码器公开(公告)号：US20080025132A1
公开(公告)日：2008-01-31
申请号：US11461364
申请日：2006-07-31
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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6.发明授权Memory array incorporating two data busses for memory array block selection 有权包含两个数据总线的存储器阵列用于存储器阵列块选择公开(公告)号：US07463536B2
公开(公告)日：2008-12-09
申请号：US11461359
申请日：2006-07-31
IPC分类号： G11C8/12
CPC分类号： G11C17/18 , G11C5/063 , G11C7/1048 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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7.发明申请公开(公告)号：US20080025085A1
公开(公告)日：2008-01-31
申请号：US11461359
申请日：2006-07-31
IPC分类号： G11C16/04
CPC分类号： G11C17/18 , G11C5/063 , G11C7/1048 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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公开(公告)号：US07570523B2
公开(公告)日：2009-08-04
申请号：US11461372
申请日：2006-07-31
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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公开(公告)号：US07272052B2
公开(公告)日：2007-09-18
申请号：US11146952
申请日：2005-06-07
IPC分类号： G11C16/06
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译： 公开了一种用于非二进制组的存储器线驱动器的解码电路。 在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。 在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一 。 控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。 本文所述的概念可以单独使用或组合使用。
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10.发明授权Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same 有权提供存储器阵列操作的正向和反向模式的解码器电路以及用于对其进行偏置的方法公开(公告)号：US08279704B2
公开(公告)日：2012-10-02
申请号：US12895523
申请日：2010-09-30
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/00
CPC分类号： G11C7/18 , G11C7/1048 , G11C8/08 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译： 描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。 此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元 并且用于将未选择的偏置条件传送到未选择的阵列块。
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