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公开(公告)号：US09336835B2
公开(公告)日：2016-05-10
申请号：US14016250
申请日：2013-09-03
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。
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公开(公告)号：US20140071757A1
公开(公告)日：2014-03-13
申请号：US14016250
申请日：2013-09-03
IPC分类号： G11C16/08
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。
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公开(公告)号：US08881389B2
公开(公告)日：2014-11-11
申请号：US13457170
申请日：2012-04-26
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。
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4.发明授权公开(公告)号：US08189328B2
公开(公告)日：2012-05-29
申请号：US11876479
申请日：2007-10-22
IPC分类号： H05K7/00
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one embodiment of the invention, a flash memory dual inline memory module (FMDIMM) is disclosed. The FMDIMM includes a printed circuit board (PCB) with an edge connector; a first plurality of multi-chip packaged flash memory/support application specific integrated circuit (ASIC) parts mounted to the printed circuit board and electrically coupled to the edge connector; and a first address device mounted to the PCB and electrically coupled to the edge connector and the first plurality of multi-chip packaged flash memory/support ASIC parts. Each of the first plurality of multi-chip packaged flash memory/support ASIC parts includes one or more randomly accessible flash memory die to periodically store data in a non-volatile manner.
摘要翻译： 在本发明的一个实施例中，公开了一种闪存双列直插存储器模块（FMDIMM）。 FMDIMM包括具有边缘连接器的印刷电路板（PCB）; 安装到印刷电路板并电耦合到边缘连接器的第一多个多芯片封装的闪存/支持专用集成电路（ASIC）部件; 以及安装到PCB并电耦合到边缘连接器和第一多个多芯片封装的闪存/支持ASIC部分的第一地址设备。 第一多个多芯片封装的闪存/支持ASIC部件中的每一个包括一个或多个随机可访问的闪存芯片，以不稳定的方式周期性地存储数据。
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5.发明授权Multi-chip packaged flash memory/support application specific integrated circuit for flash dual inline memory modules 有权多芯片封装闪存/支持应用专用集成电路，用于闪存双列直插内存模块公开(公告)号：US09318156B2
公开(公告)日：2016-04-19
申请号：US14016235
申请日：2013-09-03
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。
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6.发明申请MULTI-CHIP PACKAGED FLASH MEMORY/SUPPORT APPLICATION SPECIFIC INTEGRATED CIRCUIT FOR FLASH DUAL INLINE MEMORY MODULES 有权多芯片封装FLASH存储器/支持应用特殊集成电路，用于闪存双内存模块公开(公告)号：US20140071610A1
公开(公告)日：2014-03-13
申请号：US14016235
申请日：2013-09-03
IPC分类号： G11C5/04
CPC分类号： G11C16/30 , G11C5/04 , G11C5/14 , G11C16/08 , H01R12/725 , H05K1/0286 , H05K1/181 , H05K2201/10159 , H05K2201/10212 , Y02P70/611 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49169
摘要： In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.
摘要翻译： 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。
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7.发明授权Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices 有权用于交错启动预定义，随机或动态数量的闪存设备的方法和装置公开(公告)号：US08625353B2
公开(公告)日：2014-01-07
申请号：US13162520
申请日：2011-06-16
IPC分类号： G11C16/04
CPC分类号： G11C16/32 , G06F3/0604 , G06F3/0632 , G06F3/0679 , G11C16/30
摘要： A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.
摘要翻译： 提供了一种用于存储器件启动的方法，装置和制造。 闪存器件被配置为使得在电源电压达到预定电平时，每个闪存被布置成以闪存的指令加载随机存取存储器，然后执行用于闪存的指令的第一部分 记忆。 在执行闪速存储器的指令的第一部分之后，闪速存储器的每个单独的子集等待单独的，不同的延迟周期。 对于每个闪存，在该闪速存储器的延迟时间期满之后，闪速存储器执行闪速存储器指令的第二部分。
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公开(公告)号：US20100274959A1
公开(公告)日：2010-10-28
申请号：US12832409
申请日：2010-07-08
CPC分类号： G06F13/4009 , G06F12/0638 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译： 公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。 多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。 可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。 存储器控制器控制对非易失性存储器模块的读取和写入访问。 存储器插座通过印刷电路板迹线耦合到处理器插座。 用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。
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公开(公告)号：US08364867B2
公开(公告)日：2013-01-29
申请号：US12831206
申请日：2010-07-06
IPC分类号： G06F13/12
CPC分类号： G06F13/1657 , Y02D10/14
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces.The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译： 公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。 多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。 可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。 存储器控制器控制对非易失性存储器模块的读取和写入访问。 存储器插座通过印刷电路板迹线耦合到处理器插座。 用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。
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10.发明申请METHODS OF ASSEMBLY OF A COMPUTER SYSTEM WITH RANDOMLY ACCESSIBLE NON-VOLATILE MEMORY 有权具有随机可访问的非易失性存储器的计算机系统的组装方法公开(公告)号：US20100274958A1
公开(公告)日：2010-10-28
申请号：US12832921
申请日：2010-07-08
CPC分类号： G06F13/1657 , Y02D10/14
摘要： An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
摘要翻译： 一种装置包括具有多个印刷电路板迹线的印刷电路板，安装在与多个印刷电路板迹线中的一个或多个印刷电路板迹线耦合的印刷电路板上的存储器控制器，多个非易失型存储器集成电路 耦合到印刷电路板，以及耦合在存储器控制器和多个非易失性类型的存储器集成电路之间的多个支持集成电路。
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