公开(公告)号：US08028031B2

公开(公告)日：2011-09-27

申请号：US12147490

申请日：2008-06-27

申请人： Ryan Colvin ,  Chad Mills ,  Robert McCann ,  Geoff Hulten ,  Harry Katz ,  Eriola Kruja ,  Xin Huang ,  Joshua Korb

发明人： Ryan Colvin ,  Chad Mills ,  Robert McCann ,  Geoff Hulten ,  Harry Katz ,  Eriola Kruja ,  Xin Huang ,  Joshua Korb

IPC分类号： G06F15/16 ,  G06F12/00

CPC分类号： G06Q10/107 ,  H04L51/12

摘要： Determining email filtering type based on sender classification. Incoming email is accessed and a sender of the incoming email is identified. The reputation of the sender of the incoming email is determined. An email sender classification is made based on the reputation of the sender. A determination of the type of filtering operations to be performed by an email filter on the email is made based on the classification. The parameters of the type of filtering operations to be performed are determined. The parameters of the type of filtering operations to be performed are provided to the email filter.

摘要翻译： 根据发送者分类确定电子邮件过滤类型。 访问收到的电子邮件，并确定收到的电子邮件的发件人。 确定传入电子邮件的发件人的声誉。 电子邮件发送者分类是根据发信人的声誉进行的。 基于分类确定由电子邮件过滤器执行的过滤操作的类型。 确定要执行的过滤操作的类型的参数。 将要执行的过滤操作的类型的参数提供给电子邮件过滤器。

公开(公告)号：USD1005611S1

公开(公告)日：2023-11-21

申请号：US29850956

申请日：2022-08-24

申请人： Xin Huang

设计人： Xin Huang

摘要： FIG. 1 is a front and bottom perspective view of a pet harness, showing my new design;
FIG. 2 is a rear and top perspective view thereof;
FIG. 3 is a front elevation view thereof;
FIG. 4 is a rear elevation view thereof;
FIG. 5 is a left side elevation view thereof;
FIG. 6 is a right side elevation view thereof;
FIG. 7 is a top plan view thereof;
FIG. 8 is a bottom plan view thereof;
FIG. 9 is another perspective view of the pet harness, shown in an alternative position;
FIG. 10 is an enlarged perspective view of detail “10” identified in FIG. 2; and,
FIG. 11 is an enlarged perspective view of detail “11” identified in FIG. 4.
The dashed lines in the figures illustrate portions of the pet harness that form no part of the claimed design. The dash dot dash lines in FIGS. 2, 4, 10 and 11 are for the purpose of depicting the boundary lines of the enlarged views and form no part of the claimed design.

公开(公告)号：US08902918B2

公开(公告)日：2014-12-02

申请号：US13449967

申请日：2012-04-18

申请人： Xin Huang ,  Dingzhang Dai ,  Hongwei Wang ,  Fangfu Guo

发明人： Xin Huang ,  Dingzhang Dai ,  Hongwei Wang ,  Fangfu Guo

IPC分类号： H04J3/16 ,  H04J3/22 ,  H04L1/18 ,  H04L1/00

CPC分类号： H04L1/1825 ,  H04L1/0015 ,  H04L1/1883

摘要： An embodiment of the present invention discloses a high speed uplink packet access adaptive retransmission method and apparatus. The method includes: obtaining a resource limitation state; performing adjustment decision according to the resource limitation state and a current target number of retransmissions of a UE; and adjusting the target number of retransmissions of the UE between a preset large target number of retransmissions and a preset small target number of retransmissions, where the large target number of retransmissions is greater than the small target number of retransmissions. The utilization rate of resources may be effectively improved.

摘要翻译： 本发明的实施例公开了一种高速上行分组接入自适应重传方法和装置。 该方法包括：获取资源限制状态; 根据资源限制状态和UE的当前目标重传次数进行调整决定; 以及在预设的大目标重发次数与预定的小目标重发次数之间调整所述UE的目标重传次数，其中所述大目标重发次数大于所述小目标重传次数。 资源利用率可以有效提高。

公开(公告)号：USD713041S1

公开(公告)日：2014-09-09

申请号：US29428197

申请日：2012-07-27

申请人： Junwei Xu ,  Xin Huang ,  Tengfei Yang

设计人： Junwei Xu ,  Xin Huang ,  Tengfei Yang

公开(公告)号：US08722325B2

公开(公告)日：2014-05-13

申请号：US13480358

申请日：2012-05-24

申请人： Susanne M. Gollin ,  Rahul Atul Parikh ,  Xin Huang

发明人： Susanne M. Gollin ,  Rahul Atul Parikh ,  Xin Huang

IPC分类号： C12Q1/68

CPC分类号： C12Q1/6886 ,  G01N33/5091 ,  G01N33/57484

摘要： The present invention relates to the discovery that, in human cancer, an 11q deletion of ATM together with an increase in ATR and CHEK1 expression correlates with resistance to ionizing radiation which could be overcome by inhibition of the ATR/CHEK1 pathway. It provides for methods of identifying patients unlikely to exhibit an adequate response to radiation therapy and/or chemotherapy who may benefit from ATR/CHEK1 pathway inhibition, as well as methods of treating said patients.

摘要翻译： 本发明涉及这样的发现：在人类癌症中，ATM的11q缺失与ATR和CHEK1表达的增加一起与电离辐射的抗性相关，可以通过抑制ATR / CHEK1途径来克服。 它提供了鉴定不太可能对可能受益于ATR / CHEK1途径抑制的放射治疗和/或化学疗法表现出足够反应的患者的方法，以及治疗所述患者的方法。

公开(公告)号：US08598636B2

公开(公告)日：2013-12-03

申请号：US13582624

申请日：2011-08-17

申请人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

发明人： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

IPC分类号： H01L29/80

CPC分类号： H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.

摘要翻译： 本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。 散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。 在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线 漏极端子相对于漏极端子施加低电位。 在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是 相对于源极端子施加较低的电位。 通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此 在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

公开(公告)号：US08563370B2

公开(公告)日：2013-10-22

申请号：US13384215

申请日：2011-07-04

申请人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

发明人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC分类号： H01L21/338

CPC分类号： H01L29/78696 ,  H01L21/76289 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772

摘要： A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

摘要翻译： 提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。 该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

公开(公告)号：US20130017654A1

公开(公告)日：2013-01-17

申请号：US13266791

申请日：2011-07-15

申请人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

发明人： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC分类号： H01L21/336 ,  B82Y99/00

CPC分类号： H01L29/66439 ,  B82Y10/00 ,  H01L29/775

摘要： The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.

摘要翻译： 本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。 该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。 本发明与CMOS工艺流程兼容。 空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

公开(公告)号：US20120302027A1

公开(公告)日：2012-11-29

申请号：US13511123

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

摘要翻译： 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

公开(公告)号：US20120168770A1

公开(公告)日：2012-07-05

申请号：US13391270

申请日：2011-11-18

申请人： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

发明人： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

IPC分类号： H01L29/20 ,  H01L29/12

CPC分类号： H01L23/38 ,  H01L23/3738 ,  H01L2924/0002 ,  H01L2924/00

摘要： A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.

摘要翻译： 提供了微电子领域的芯片的散热结构。 散热结构包括通过氧化隔离在芯片的上表面上形成的P型超晶格层和N型超晶格层。 P型超晶格和N型超晶格被氧化硅隔离。 通过接触孔，P型超晶格与在芯片中施加低电位的金属层电连接，并且在P型超晶格上形成与外部电源连接的金属层。 通过接触孔，N型超晶格电连接到在芯片中施加高电位电源的金属层，并且在N型超晶格上形成与外部电源连接的金属层 。 与P型超晶格连接的外部电源的电位低于与N型超晶格连接的外部电源的电位。 本发明可以实现芯片的散热，同时通过使用超晶格具有低导热性和声子定位的特性的特征，同时防止环境热量转移到芯片中。