公开(公告)号：US08901644B2

公开(公告)日：2014-12-02

申请号：US13821944

申请日：2011-09-09

Applicant: Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

Inventor： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/775 ,  H01L29/06 ,  H01L21/28 ,  H01L29/41 ,  H01L29/423

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/2815 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract translation: 本文公开了具有垂直沟道的场效应晶体管及其制造方法。 场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口， 在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。 与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

公开(公告)号：US08592276B2

公开(公告)日：2013-11-26

申请号：US13501711

申请日：2011-11-18

Applicant: Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

Inventor： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC: H01L21/336

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract translation: 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

公开(公告)号：US09034702B2

公开(公告)日：2015-05-19

申请号：US13511123

申请日：2011-11-18

Applicant: Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

Inventor： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

Abstract translation: 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

公开(公告)号：US08722312B2

公开(公告)日：2014-05-13

申请号：US13379752

申请日：2011-09-09

Applicant: Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

Inventor： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

IPC: G03F7/20

CPC classification number: B82Y40/00

Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

Abstract translation: 本发明公开了一种制造半导体纳米圆环的方法。 在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。 然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。 本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本 环状纳米结构。

公开(公告)号：US08372752B1

公开(公告)日：2013-02-12

申请号：US13543704

申请日：2012-07-06

Applicant: Ru Huang ,  Shuai Sun ,  Yujie Al ,  Jiewen Fan ,  Runsheng Wang ,  Xiaoyan Xu

Inventor： Ru Huang ,  Shuai Sun ,  Yujie Al ,  Jiewen Fan ,  Runsheng Wang ,  Xiaoyan Xu

IPC: H01L21/302 ,  H01L21/461

CPC classification number: B82Y40/00 ,  H01L29/0676

Abstract: Disclosed herein is a method for fabricating an ultra fine nanowire, which relates to a manufacturing technology of a microelectronic semiconductor transistor. This method obtains a suspended ultra fine nanowire base on a combination of a mask blocking oxidation process and a stepwise oxidation process. A diameter of the suspended ultra fine nanowire fabricated by this method is precisely controlled to 20 nm by controlling a thickness of a deposited silicon nitride film and a time and temperature of the two oxidation process. Since a speed of a dry oxidation process is slower, the size of the final nanowire may be precisely controlled. This method can be used to fabricate an ultra fine nanowire with a lower cost and a higher applicability.

Abstract translation: 本文公开了一种制造超细纳米线的方法，涉及微电子半导体晶体管的制造技术。 该方法通过掩模阻挡氧化工艺和逐步氧化工艺的组合获得悬浮的超细纳米线基底。 通过控制沉积的氮化硅膜的厚度和两个氧化过程的时间和温度，将通过该方法制造的悬浮超细纳米线的直径精确控制为20nm。 由于干燥氧化工艺的速度较慢，可以精确地控制最终纳米线的尺寸。 该方法可用于制造具有较低成本和较高适用性的超细纳米线。

公开(公告)号：US20130130503A1

公开(公告)日：2013-05-23

申请号：US13511624

申请日：2012-02-03

Applicant: Ru Huang ,  Shuai Sun ,  Yujie Ai ,  Jiewen Fan ,  Runsheng Wang ,  Xiaoyan Xu

Inventor： Ru Huang ,  Shuai Sun ,  Yujie Ai ,  Jiewen Fan ,  Runsheng Wang ,  Xiaoyan Xu

IPC: H01L21/308 ,  B82Y40/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/0673

Abstract: Disclosed herein is a method for fabricating an ultra-fine nanowire by combining a trimming process and a mask blocking oxidation process. The ultra-thin nanowire is fabricated by a combination of performing a trimming process on a mask to reduce a width of the mask and blocking an oxidation through the mask. A diameter of the floated ultra-thin nanowire fabricated by the method is controlled to 20 nm below by a thickness of a deposited silicon oxide film, a width of the silicon oxide nanowire after trimming, and a time and a temperature for performing a wet oxidation process. Also, since a speed of the wet oxidation process is faster, the width of the nanowire obtained by a conventional photolithography is reduced faster. Moreover, when fabricating an ultra-thin nanowire by using the method, the cost is reduced and it is more feasible to be implemented.

Abstract translation: 本文公开了通过组合修整工艺和掩模阻挡氧化工艺来制造超细纳米线的方法。 超薄纳米线通过对掩模进行修整处理以减少掩模的宽度并阻挡通过掩模的氧化的组合来制造。 通过该方法制造的漂浮的超薄纳米线的直径通过沉积的氧化硅膜的厚度，修整后的氧化硅纳米线的宽度以及进行湿氧化的时间和温度控制在20nm以下 处理。 此外，由于湿式氧化处理的速度更快，所以通过常规光刻获得的纳米线的宽度更快地降低。 此外，当通过使用该方法制造超薄纳米线时，成本降低，并且更可行。

公开(公告)号：US20120302027A1

公开(公告)日：2012-11-29

申请号：US13511123

申请日：2011-11-18

Applicant: Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

Inventor： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

Abstract translation: 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

公开(公告)号：US20130168759A1

公开(公告)日：2013-07-04

申请号：US13821944

申请日：2011-09-09

Applicant: Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

Inventor： Ru Huang ,  Yujie Ai ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xiaoyan Xu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/2815 ,  H01L29/04 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/413 ,  H01L29/42376 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775

Abstract: Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.

Abstract translation: 本文公开了具有垂直沟道的场效应晶体管及其制造方法。 场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口， 在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。 与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

公开(公告)号：US20130011980A1

公开(公告)日：2013-01-10

申请号：US13501711

申请日：2011-11-18

Applicant: Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

Inventor： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract translation: 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

公开(公告)号：US20120190202A1

公开(公告)日：2012-07-26

申请号：US13379752

申请日：2011-09-09

Applicant: Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

Inventor： Ru Huang ,  Yujie Al ,  Zhihua Hao ,  Shuangshuang Pu ,  Jiewen Fan ,  Shuai Sun ,  Runsheng Wang ,  Xia An

IPC: H01L21/311 ,  B82Y40/00

CPC classification number: B82Y40/00

Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

Abstract translation: 本发明公开了一种制造半导体纳米圆环的方法。 在该方法中，首先将正性光致抗蚀剂涂覆在半导体基板上，然后通过使用微米尺寸直径的圆形掩模曝光光致抗蚀剂，以便基于泊松衍射原理获得圆形环形光致抗蚀剂。 然后，在圆环状光致抗蚀剂的保护下，在基板上进行等离子体蚀刻，以在基板的表面上形成具有纳米尺寸壁厚的圆形环状结构。 本发明的实施例通过使用微米尺寸的光刻设备和微米尺寸的圆形掩模来制造纳米尺寸的圆环形结构，并克服了先进技术的依赖性，从而有效降低圆形的制造成本 环状纳米结构。