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    Interrupt routing within multiple-processor system
    1.
    发明申请
    Interrupt routing within multiple-processor system 审中-公开
    多处理器系统中的中断路由

    公开(公告)号：US20070239917A1

    公开(公告)日：2007-10-11

    申请号：US11299152

    申请日：2005-12-09

    申请人： Ryuji Orita ,  Mehul Shah ,  Sumeet Kochar

    发明人： Ryuji Orita ,  Mehul Shah ,  Sumeet Kochar

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： Interrupts are routed within a multiple-processor system, such as a single computing device having multiple processors. Such a computerized system includes a number of processors and a mechanism. Each processor is capable of processing an interrupt. The mechanism, such as a Southbridge controller, receives the interrupt and routes it to a selected processor. The selected processor processes the interrupt via entry into a mode related to the interrupt. The interrupt may be a system management interrupt (SMI), and the mode a system management mode (SMM). The other processors operate normally and are not affected by processing of the interrupt, and do not have to enter the mode. These other processors can continue executing code as before, and may receive and process other types of interrupts. The system may include another mechanism, such as a complex programmable logic device (CPLD), specifying the selected processor.

    摘要翻译： 中断在多处理器系统中路由，例如具有多个处理器的单个计算设备。 这种计算机化系统包括多个处理器和机构。 每个处理器都能处理一个中断。 诸如南桥控制器的机制接收中断并将其路由到所选择的处理器。 所选择的处理器通过进入与中断相关的模式来处理中断。 中断可能是系统管理中断（SMI），而模式是系统管理模式（SMM）。 其他处理器正常运行，不受中断处理的影响，无需进入模式。 这些其他处理器可以像以前一样继续执行代码，并且可以接收和处理其他类型的中断。 该系统可以包括指定所选择的处理器的另一种机制，例如复杂可编程逻辑器件（CPLD）。

    Debugging module to load error decoding logic from firmware and to execute logic in response to an error
    2.
    发明授权
    Debugging module to load error decoding logic from firmware and to execute logic in response to an error 有权
    调试模块从固件加载错误解码逻辑，并响应错误执行逻辑

    公开(公告)号：US08504875B2

    公开(公告)日：2013-08-06

    申请号：US12647828

    申请日：2009-12-28

    申请人： Ryuji Orita ,  Barry A. Kritt ,  Charles D. Bauman ,  Sumeet Kochar ,  Jeremy K. Holland ,  Karen A. Taylor

    发明人： Ryuji Orita ,  Barry A. Kritt ,  Charles D. Bauman ,  Sumeet Kochar ,  Jeremy K. Holland ,  Karen A. Taylor

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0793

    摘要： A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.

    摘要翻译： 计算设备包括处理器，固件，硬件组件和调试模块。 固件存储特定于计算设备的错误解码逻辑。 硬件组件检测计算设备中的错误，并且响应地发出中断并停止处理器，使得处理器不能执行任何更多的计算机可读代码。 调试模块在复位时从固件加载逻辑，并响应中断执行逻辑。 调试模块不使用处理器执行逻辑，固件不是调试模块的一部分，调试模块不是硬件组件的一部分。 固件还可以存储硬件组件的寄存器和计算设备的现场可替换硬件单元之间的映射，调试模块在执行错误解码逻辑以确定哪个单元已经引起错误时在复位时加载并使用。

    Managing Power Consumption Of A Computer
    3.
    发明申请
    Managing Power Consumption Of A Computer 失效
    管理计算机的功耗

    公开(公告)号：US20120284540A1

    公开(公告)日：2012-11-08

    申请号：US13546090

    申请日：2012-07-11

    申请人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcom S. Ware

    发明人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcom S. Ware

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203

    摘要： Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

    摘要翻译： 用于管理计算机的功耗的方法，计算机和产品，包括计算机处理器的计算机和管理计算机的功耗的方法，计算机和产品包括：在计算机运行期间动态地根据性能度量由带内功率管理器进行设置 计算机处理器的当前性能状态（p状态）; 以及由所述带内功率管理器向所述带外功率管理器提供所述计算机处理器的当前p状态。

    Managing power consumption of a computer
    4.
    发明授权
    Managing power consumption of a computer 有权
    管理电脑的功耗

    公开(公告)号：US08103884B2

    公开(公告)日：2012-01-24

    申请号：US12146085

    申请日：2008-06-25

    申请人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    发明人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  Y02D10/16

    摘要： Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.

    摘要翻译： 用于管理计算机和功耗管理的计算机的功耗的方法和产品。 计算机包括包括计算机处理器的计算机，并且本发明的实施例包括通过带内功率管理器向带外功率管理器提供用于计算机处理器的建议的性能状态（“p状态”） ; 由带外功率管理器根据功率设定点和计算机处理器的当前测量的操作度量来确定是否批准所提出的p状态; 并且如果带外功率管理器批准所提出的p状态，则根据批准的p状态来设置计算机处理器的操作参数。

    Debugging module to load error decoding logic from firmware and to execute logic in response to an error
    5.
    发明申请
    Debugging module to load error decoding logic from firmware and to execute logic in response to an error 有权
    调试模块从固件加载错误解码逻辑，并响应错误执行逻辑

    公开(公告)号：US20110161736A1

    公开(公告)日：2011-06-30

    申请号：US12647828

    申请日：2009-12-28

    申请人： Ryuji Orita ,  Barry A. Kritt ,  Charles D. Bauman ,  Sumeet Kochar ,  Jeremy K. Holland ,  Karen A. Taylor

    发明人： Ryuji Orita ,  Barry A. Kritt ,  Charles D. Bauman ,  Sumeet Kochar ,  Jeremy K. Holland ,  Karen A. Taylor

    IPC分类号： G06F11/07 ,  G06F9/44

    CPC分类号： G06F11/0793

    摘要： A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.

    摘要翻译： 计算设备包括处理器，固件，硬件组件和调试模块。 固件存储特定于计算设备的错误解码逻辑。 硬件组件检测计算设备中的错误，并且响应地发出中断并停止处理器，使得处理器不能执行任何更多的计算机可读代码。 调试模块在复位时从固件加载逻辑，并响应中断执行逻辑。 调试模块不使用处理器执行逻辑，固件不是调试模块的一部分，调试模块不是硬件组件的一部分。 固件还可以存储硬件组件的寄存器和计算设备的现场可替换硬件单元之间的映射，调试模块在执行错误解码逻辑以确定哪个单元已经引起错误时在复位时加载并使用。

    Managing Power Consumption Of A Computer
    8.
    发明申请
    Managing Power Consumption Of A Computer 有权
    管理计算机的功耗

    公开(公告)号：US20090327765A1

    公开(公告)日：2009-12-31

    申请号：US12146085

    申请日：2008-06-25

    申请人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    发明人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  Y02D10/16

    摘要： Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.

    摘要翻译： 用于管理计算机和功耗管理的计算机的功耗的方法和产品。 计算机包括包括计算机处理器的计算机，并且本发明的实施例包括通过带内功率管理器向带外功率管理器提供用于计算机处理器的建议的性能状态（“p状态”） ; 由带外功率管理器根据功率设定点和计算机处理器的当前测量的操作度量来确定是否批准所提出的p状态; 并且如果带外功率管理器批准所提出的p状态，则根据批准的p状态来设置计算机处理器的操作参数。

    Managing Power Consumption Of A Computer
    9.
    发明申请
    Managing Power Consumption Of A Computer 有权
    管理计算机的功耗

    公开(公告)号：US20090327764A1

    公开(公告)日：2009-12-31

    申请号：US12146056

    申请日：2008-06-25

    申请人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    发明人： Thomas M. Brey ,  Wesley M. Felter ,  Sumeet Kochar ,  Charles R. Lefurgy ,  Ryuji Orita ,  Freeman L. Rawson, III ,  Malcolm S. Ware

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203

    摘要： Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

    摘要翻译： 用于管理计算机的功耗的方法，计算机和产品，包括计算机处理器的计算机和管理计算机的功耗的方法，计算机和产品包括：在计算机运行期间动态地根据性能度量由带内功率管理器进行设置 计算机处理器的当前性能状态（'p状态'）; 以及由所述带内功率管理器向所述带外功率管理器提供所述计算机处理器的当前p状态。

    MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS
    10.
    发明申请
    MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS 审中-公开
    管理用于LEGACY操作系统的PCI-EXPRESS MAX PAYLOAD SIZE

    公开(公告)号：US20100064080A1

    公开(公告)日：2010-03-11

    申请号：US12208640

    申请日：2008-09-11

    申请人： Mehul Shah ,  Ryuji Orita ,  Sandra D. Rhodes

    发明人： Mehul Shah ,  Ryuji Orita ,  Sandra D. Rhodes

    IPC分类号： G06F13/42

    CPC分类号： G06F13/4221

    摘要： The present disclosure is directed to a method for balancing latency versus bandwidth trade-offs in packet transmission utilizing PCI-Express. The method may comprise identifying at least one system element along a path of a packet to be transmitted; determining and storing an optimum payload size for each one of the at least one system element; configuring a Max Payload Size parameter for each one of the at least one system element, wherein the Max Payload Size parameter is configured based on the optimum payload size for each one of the at least one system element.

    摘要翻译： 本公开涉及一种利用PCI-Express在分组传输中平衡等待时间与带宽折衷的方法。 该方法可以包括沿着待发送的分组的路径识别至少一个系统元件; 确定和存储所述至少一个系统元件中的每一个的最佳有效载荷大小; 为所述至少一个系统元件中的每个系统元件配置最大有效载荷大小参数，其中所述最大有效载荷大小参数基于所述至少一个系统元件中的每个系统元件的最佳有效载荷大小来配置。