公开(公告)号：US20100084709A1

公开(公告)日：2010-04-08

申请号：US11993862

申请日：2006-06-30

申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/86

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。 另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。 使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜 并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。 由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。 可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

公开(公告)号：US20080258218A1

公开(公告)日：2008-10-23

申请号：US12105226

申请日：2008-04-17

申请人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/01

CPC分类号： H01L29/045 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.

摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。

公开(公告)号：US20060081836A1

公开(公告)日：2006-04-20

申请号：US11249681

申请日：2005-10-14

申请人： Yoshinobu Kimura ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Ryuta Tsuchiya ,  Shinichi Saito

发明人： Yoshinobu Kimura ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Ryuta Tsuchiya ,  Shinichi Saito

IPC分类号： H01L31/109

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

摘要： In a field effect semiconductor device for high frequency power amplification, it is difficult to achieve size reduction and increased efficiency simultaneously while ensuring voltage withstanding. A further improvement in efficiency is attained by using a strained Si channel for LDMOS at an output stage for high frequency power amplification. Further, the efficiency is improved as much as possible while decreasing a leak current, by optimizing the film thickness of the strained Si layer having a channel region, inactivation of defects and a field plate structure.

摘要翻译： 在用于高频功率放大的场效半导体器件中，难以在确保耐压的同时实现尺寸减小和提高效率。 通过在高频功率放大的输出级使用用于LDMOS的应变Si通道来实现效率的进一步提高。 此外，通过优化具有通道区域的应变Si层的膜厚度，缺陷的失活和场板结构，尽可能地提高效率同时减小漏电流。

公开(公告)号：US08183115B2

公开(公告)日：2012-05-22

申请号：US13088020

申请日：2011-04-15

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在所述栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比第二升高层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US20100258869A1

公开(公告)日：2010-10-14

申请号：US12757090

申请日：2010-04-09

申请人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).

摘要翻译： 形成在具有薄BOX层的SOI衬底的主表面上以预定间隔布置的n阱和p阱，并且在p阱上形成的nMIS具有形成在半导体层上的一对n型源极/漏极区 堆叠在SOI层的主表面上，预定距离处，栅极绝缘膜，栅电极和夹在该对n型源极/漏极区之间的侧壁。 在n阱和p阱之间形成器件隔离，并且器件隔离的侧边缘部分比n型源极/漏极区域的侧边缘部分（BOX层的侧壁）朝向栅电极侧延伸 ）。

公开(公告)号：US08183635B2

公开(公告)日：2012-05-22

申请号：US12756451

申请日：2010-04-08

申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/76283

摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

公开(公告)号：US08643117B2

公开(公告)日：2014-02-04

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US08409936B2

公开(公告)日：2013-04-02

申请号：US13363268

申请日：2012-01-31

申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 一种器件及其制造方法，其中，器件包括单晶半导体衬底和通过薄的掩埋绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的SOI衬底 以相同的步骤形成SOI型MISFET和体型MISFET的良好扩散层区域，漏极区域，栅极绝缘膜和栅极电极。 本体型MISFET和SOI型MISFET形成在同一衬底上，从而通过制造SOI型MISFET和体型MISFET的制造步骤，可以减少电路板面积并简化工艺。

公开(公告)号：US20090096036A1

公开(公告)日：2009-04-16

申请号：US12248250

申请日：2008-10-09

申请人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US20090057746A1

公开(公告)日：2009-03-05

申请号：US12187504

申请日：2008-08-07

申请人： Nobuyuki Sugll ,  Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Nobuyuki Sugll ,  Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/788 ,  H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0629 ,  H01L29/93

摘要： A semiconductor device having a passive element whose characteristic is adjustable even after manufacture by applying back bias voltage is provided. Formed on a main surface of a SOI substrate comprising a supporting substrate, a BOX layer, and an SOI layer is a MOS varactor comprising a gate dielectric formed on a surface of the SOI layer, a gate electrode formed on the gate dielectric, and a n+ type semiconductor region formed in the SOI layer located on both sides of the gate electrode. The MOS varactor, is configured so that capacitance formed by the SOI layer, gate dielectric, and gate electrode is varied by applying bias voltage to the supporting substrate (p type well) under the gate electrode.

摘要翻译： 提供了一种具有无源元件的半导体器件，其特征是即使在通过施加反向偏置电压制造之后也是可调节的。 在包括支撑衬底，BOX层和SOI层的SOI衬底的主表面上形成MOS变容二极管，其包括在SOI层的表面上形成的栅极电介质，形成在栅极电介质上的栅电极和 n +型半导体区域形成在位于栅电极两侧的SOI层中。 MOS变容二极管被配置为使得由SOI层，栅极电介质和栅电极形成的电容通过在栅电极下施加偏置电压到支撑衬底（p型阱）来改变。