利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.036 秒)

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20080258218A1

    公开(公告)日：2008-10-23

    申请号：US12105226

    申请日：2008-04-17

    申请人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

    发明人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

    IPC分类号： H01L27/01

    CPC分类号： H01L29/045 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.

    摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08183635B2

    公开(公告)日：2012-05-22

    申请号：US12756451

    申请日：2010-04-08

    申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

    发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

    IPC分类号： H01L21/00

    CPC分类号： H01L27/1203 ,  H01L21/76283

    摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

    摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

    SiGe MOSFET semiconductor device with sloped source/drain regions
    7.
    发明授权
    SiGe MOSFET semiconductor device with sloped source/drain regions 有权
    具有倾斜源极/漏极区域的SiGe MOSFET半导体器件

    公开(公告)号：US08143668B2

    公开(公告)日：2012-03-27

    申请号：US12481551

    申请日：2009-06-09

    申请人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

    发明人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823814 ,  H01L21/823828 ,  H01L21/823864

    摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

    摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120061774A1

    公开(公告)日：2012-03-15

    申请号：US13299471

    申请日：2011-11-18

    申请人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

    发明人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823814 ,  H01L21/823828 ,  H01L21/823864

    摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

    摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。

    Semiconductor device, method for manufacturing same, and semiconductor storage device
    10.
    发明授权
    Semiconductor device, method for manufacturing same, and semiconductor storage device 有权
    半导体装置及其制造方法以及半导体存储装置

    公开(公告)号：US08643117B2

    公开(公告)日：2014-02-04

    申请号：US13145108

    申请日：2010-01-18

    申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

    发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

    IPC分类号： H01L21/70

    CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

    摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

    摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。