公开(公告)号：US20220077267A1

公开(公告)日：2022-03-10

申请号：US17318350

申请日：2021-05-12

Applicant: Samsung Display Co., Ltd.

Inventor： HYUNGJUN KIM ,  SOYOUNG KOO ,  EOK SU KIM ,  YUNYONG NAM ,  JUN HYUNG LIM ,  KYUNGJIN JEON

IPC: H01L27/32 ,  H01L51/56

Abstract: A display device includes a first transistor including a first transistor including a light blocking pattern on a substrate, an active pattern on the light blocking pattern, and a gate electrode on the active pattern, a second transistor configured to provide a data voltage to the first transistor in response to a gate signal, and a storage capacitor electrically connected to the gate electrode and the light blocking pattern, and including a first conductive pattern in a same layer as the light blocking pattern, a second conductive pattern on the first conductive pattern and overlapping the first conductive pattern, a third conductive pattern in a same layer as the gate electrode, overlapping the second conductive pattern, and electrically connected to the first conductive pattern, and a fourth conductive pattern on the third conductive pattern, overlapping the third conductive pattern, and electrically connected to the second conductive pattern.

公开(公告)号：US20250140141A1

公开(公告)日：2025-05-01

申请号：US18926720

申请日：2024-10-25

Applicant: Samsung Display Co., LTD.

Inventor： EOK SU KIM ,  SOYOUNG KOO ,  JONGDO KEUM ,  HYUNGJUN KIM ,  GEUNCHUL PARK

IPC: G09G3/00 ,  G09G3/3266 ,  H10K59/131

Abstract: A test circuit includes: a metal pattern disposed in a first area; a test gate driver disposed in a second area adjacent to the first area and including a plurality of test stages, each of which outputs a test gate signal; and a plurality of test gate lines overlapping the metal pattern in a plan view, connected to the plurality of test stages, respectively, each including a first metal line and a second metal line connected in series with the first metal line, and which receives the test gate signal.

公开(公告)号：US20240257724A1

公开(公告)日：2024-08-01

申请号：US18513917

申请日：2023-11-20

Applicant: Samsung Display Co., LTD.

Inventor： EOK SU KIM ,  JONGDO KEUM ,  TAESANG KIM

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2310/0267 ,  G09G2310/0294 ,  G09G2310/061 ,  G09G2310/08

Abstract: A gate driving circuit includes: a first pull-up control circuit, a pull-up circuit, a pull-down circuit and an inverting circuit. The first pull-up control circuit applies a previous carry signal which is one of carry signals of previous stages to a first control node in response to the previous carry signal. The pull-up circuit outputs a gate clock signal as a gate output signal in response to a signal of the first control node. The pull-down circuit outputs a second low voltage as the gate output signal in response to a first next carry signal which is one of carry signals of next stages. The inverting circuit outputs one of a first signal and a first low voltage to a third control node in response to the first signal and a signal of a second control node.

公开(公告)号：US20250151524A1

公开(公告)日：2025-05-08

申请号：US19019252

申请日：2025-01-13

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HYUNGJUN KIM ,  SOYOUNG KOO ,  EOK SU KIM ,  YUNYONG NAM ,  JUN HYUNG LIM ,  KYUNGJIN JEON

IPC: H10K59/121 ,  H10K59/12 ,  H10K59/123 ,  H10K59/126 ,  H10K71/00

Abstract: A display device includes a first transistor including a first transistor including a light blocking pattern on a substrate, an active pattern on the light blocking pattern, and a gate electrode on the active pattern, a second transistor configured to provide a data voltage to the first transistor in response to a gate signal, and a storage capacitor electrically connected to the gate electrode and the light blocking pattern, and including a first conductive pattern in a same layer as the light blocking pattern, a second conductive pattern on the first conductive pattern and overlapping the first conductive pattern, a third conductive pattern in a same layer as the gate electrode, overlapping the second conductive pattern, and electrically connected to the first conductive pattern, and a fourth conductive pattern on the third conductive pattern, overlapping the third conductive pattern, and electrically connected to the second conductive pattern.

公开(公告)号：US20250148991A1

公开(公告)日：2025-05-08

申请号：US18931505

申请日：2024-10-30

Applicant: Samsung Display Co., LTD.

Inventor： EOK SU KIM

IPC: G09G3/3266 ,  G09G3/32

Abstract: A gate driver includes a plurality of stages. Each of the plurality of stages includes a common circuit which controls a voltage of a first control node, a voltage of a second control node, and a voltage of an inverted control node, and an individual circuit which outputs a plurality of scan signals in response to the voltage of the first control node and the voltage of the inverted control node. The individual circuit includes a plurality of scan buffer transistors which output a plurality of scan clock signals as the plurality of scan signals in response to the voltage of the first control node, and a scan hold transistor which maintains the plurality of scan signals at a first low voltage in response to the voltage of the inverted control node.

公开(公告)号：US20240282248A1

公开(公告)日：2024-08-22

申请号：US18530609

申请日：2023-12-06

Applicant: Samsung Display Co., Ltd.

Inventor： EOK SU KIM ,  JONGDO KEUM ,  TAESANG KIM

IPC: G09G3/32 ,  G09G3/3266

CPC classification number: G09G3/32 ,  G09G3/3266 ,  G09G2310/0267

Abstract: A scan driving circuit includes multiple stages. A j-th stage of the stages includes a buffer part electrically connected to an output terminal that operates in response to a potential of a first control node, a holding part electrically connected to the output terminal that operates in response to a potential of a second control node, and an inverter part electrically connected to the first and second control nodes that controls the potentials of the first and second nodes. The inverter part includes a control transistor including a gate electrically connected to the first control node, and a drain electrically connected to a first voltage terminal that receives a first low voltage or a second voltage terminal that receives a second low voltage. The control transistor includes a dummy gate that receives a low voltage lower than or equal to the first and second low voltages.

公开(公告)号：US20230282790A1

公开(公告)日：2023-09-07

申请号：US17973487

申请日：2022-10-25

Applicant: Samsung Display Co., Ltd.

Inventor： YUNYONG NAM ,  EOK SU KIM ,  HYUNGJUN KIM ,  JUN HYUNG LIM ,  KYUNGJIN JEON

IPC: H01L33/62 ,  H01L33/38 ,  H01L33/00 ,  H01L33/42

CPC classification number: H01L33/62 ,  H01L33/387 ,  H01L33/005 ,  H01L33/42 ,  H01L2933/0016 ,  H01L2933/0066

Abstract: Provided is a display device including a voltage line, a passivation layer disposed on the voltage line and having an undercut shape, a first connecting electrode disposed inside the undercut shape, a second connecting electrode electrically connecting the voltage line and the first connecting line, and a common electrode electrically connected to the voltage line through at least one of the first connecting electrode and the second connecting electrode.