公开(公告)号：US09515093B2

公开(公告)日：2016-12-06

申请号：US14466317

申请日：2014-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu Xun ,  Jae Woo Park ,  Jae Won Song ,  Keum Hee Lee ,  June Whan Choi

IPC: H01L29/12 ,  H01L29/10 ,  H01L27/12 ,  H01L29/417 ,  H01L21/443 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/124 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/1368 ,  G02F2001/133519 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/443 ,  H01L21/76852 ,  H01L23/53238 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

Abstract translation: 如下提供薄膜晶体管阵列面板。 栅电极设置在基板上。 半导体层设置在栅电极上。 栅极绝缘层设置在栅电极和半导体层之间。 源电极设置在半导体层的第一侧上，具有第一侧表面。 漏电极设置在半导体层的第二侧上，具有第二侧表面。 第一和第二侧表面限定了与栅电极重叠的间隔。 金属硅化物层设置在第一和第二侧表面上。 在金属硅化物层，源电极和漏电极上设置钝化层。 钝化层不与第一和第二侧表面接触。

公开(公告)号：US10032803B2

公开(公告)日：2018-07-24

申请号：US15343780

申请日：2016-11-04

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Zhu Xun ,  Jae Woo Park ,  Jae Won Song ,  Keum Hee Lee ,  June Whan Choi

IPC: H01L21/00 ,  H01L31/00 ,  H01L27/12 ,  H01L29/417 ,  H01L21/443 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532 ,  G02F1/1335 ,  G02F1/1368

Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.