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公开(公告)号：US09479156B2
公开(公告)日：2016-10-25
申请号：US14312139
申请日：2014-06-23
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
CPC分类号： H03K17/302 , G09G3/3677 , G09G2310/0286 , G09G2320/0219 , G09G2320/043 , G11C19/28
摘要： A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.
摘要翻译： 一种栅极驱动器，包括多级栅极驱动电路，其中栅极驱动电路的每一级包括被配置为响应于先前级之一的进位信号和时钟信号而生成Q结点信号的输入部分，Q节点 信号被施加到Q节点，输出部分被配置为响应于Q节点信号将栅极输出信号输出到栅极输出端子，以及电荷共享部分连接到当前级的栅极输出端子和栅极输出端子 电荷共享部件被配置为响应于选择信号在当前级的栅极输出信号和下一级之一的栅极输出信号之间进行电荷共享。
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2.发明授权公开(公告)号：US09830856B2
公开(公告)日：2017-11-28
申请号：US15351358
申请日：2016-11-14
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
IPC分类号： G06F3/038 , G09G5/00 , G09G3/3225 , G09G3/3266 , G11C19/28
CPC分类号： G09G3/3225 , G09G3/3266 , G09G2310/0264 , G09G2310/0289 , G09G2310/08 , G11C19/28
摘要： A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.
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公开(公告)号：US20170061874A1
公开(公告)日：2017-03-02
申请号：US15351358
申请日：2016-11-14
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
IPC分类号： G09G3/3225
CPC分类号： G09G3/3225 , G09G3/3266 , G09G2310/0264 , G09G2310/0289 , G09G2310/08 , G11C19/28
摘要： A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.
摘要翻译： 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。
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公开(公告)号：US09294086B2
公开(公告)日：2016-03-22
申请号：US14456995
申请日：2014-08-11
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
IPC分类号： H03K3/00 , H03K17/687 , G09G3/32 , G11C19/18 , G11C19/28
CPC分类号： H03K17/687 , G09G3/3266 , G09G2310/0286 , G09G2310/06 , G11C19/184 , G11C19/28
摘要： A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.
摘要翻译： 舞台电路包括第一驱动器，第二驱动器，第一输出单元和第二输出单元。 第一驱动器根据第一电源，提供给第一输入端的前一级的起始信号或进位信号，提供给第二输入端的第一时钟信号和第二驱动器控制第一和第二节点的电压， 提供给第三输入端的时钟信号。 第二驱动器根据第一电源控制第三节点的电压，提供给第一输入端的先前级的起始信号或进位信号，提供给第四输入端的下一级的进位信号， 和第二节点的电压。
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公开(公告)号：US20150042638A1
公开(公告)日：2015-02-12
申请号：US14456976
申请日：2014-08-11
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
IPC分类号： G09G3/36
CPC分类号： G09G3/3225 , G09G3/3266 , G09G2310/0264 , G09G2310/0289 , G09G2310/08 , G11C19/28
摘要： A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.
摘要翻译： 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。
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公开(公告)号：US20150042383A1
公开(公告)日：2015-02-12
申请号：US14456995
申请日：2014-08-11
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
IPC分类号： G09G3/14 , H03K17/687
CPC分类号： H03K17/687 , G09G3/3266 , G09G2310/0286 , G09G2310/06 , G11C19/184 , G11C19/28
摘要： A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.
摘要翻译： 舞台电路包括第一驱动器，第二驱动器，第一输出单元和第二输出单元。 第一驱动器根据第一电源，提供给第一输入端的前一级的起始信号或进位信号，提供给第二输入端的第一时钟信号和第二驱动器控制第一和第二节点的电压， 提供给第三输入端的时钟信号。 第二驱动器根据第一电源控制第三节点的电压，提供给第一输入端的先前级的起始信号或进位信号，提供给第四输入端的下一级的进位信号， 和第二节点的电压。
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公开(公告)号：US09524674B2
公开(公告)日：2016-12-20
申请号：US14456976
申请日：2014-08-11
发明人： Oh-Kyong Kwon , Yeong-Keun Kwon , Jong-Hee Kim , Ji-Sun Kim , Jae-Keun Lim , Chong-Chul Chai
CPC分类号： G09G3/3225 , G09G3/3266 , G09G2310/0264 , G09G2310/0289 , G09G2310/08 , G11C19/28
摘要： A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.
摘要翻译： 舞台电路包括第一驱动器，第二驱动器，第一输出单元，第二输出单元和控制器。 第一驱动器根据第一电源，第三电源，开始信号或前一级输入到第一输入端的进位信号来控制第一和第二节点的电压，以及提供给第二输入端的时钟信号 终奌站。 第二驱动器根据第一电源，第三电源，第一输入端和第一和第二节点的电压来控制第三和第四节点的电压。 第一输出单元根据第一电源，第二输入端和第三和第四节点的电压将输入信号输出到第一输出端。 第二输出单元根据第二电源，第二输入端和第三和第四节点的电压向第二输出端输出扫描信号。 控制器电耦合到第一输出端子和第二驱动器。
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公开(公告)号：US10467947B2
公开(公告)日：2019-11-05
申请号：US15626878
申请日：2017-06-19
发明人： Ji-Eun Park , Jae-Keun Lim , Jin-Woo Noh , Young-Wook Yoo , Hassan Kamal
摘要： A display device includes a first display region, a second display region, a first lens, and a second lens. The first display region includes a first pixel subset and may display a first image. The first image includes a first sub-image corresponding to the first pixel subset and smaller than the first image. The second display region neighbors the first display region, includes a second pixel subset, and may display a second image. The second image includes a second sub-image corresponding to the second pixel subset and smaller than the second image. The second pixel subset is not identical to the first pixel subset. The first lens may show the first sub-image without providing the entire first image. The second lens may show the second sub-image without providing the entire second image when the first lens shows the first sub-image.
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公开(公告)号：US09071230B2
公开(公告)日：2015-06-30
申请号：US14242431
申请日：2014-04-01
发明人： Jong-Hee Kim , Yeong-Keun Kwon , Ji-Sun Kim , Jae-Keun Lim , ChongChel Chai
CPC分类号： H03K3/012 , G09G3/3674 , G09G2310/0267 , G09G2310/0286 , G09G2320/043 , G11C19/28
摘要： A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.
摘要翻译： 一种栅极驱动电路和具有栅极驱动电路的显示装置，其中栅极驱动电路包括使用低时钟信号的电压调节部分，以增加栅极驱动电路的可靠性，从而延长栅极驱动电路的寿命。
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公开(公告)号：US09875683B2
公开(公告)日：2018-01-23
申请号：US14993051
申请日：2016-01-11
发明人： Jae-Keun Lim , Ji-Hye Lee , Yong-Koo Her
IPC分类号： G09G3/32 , G09G3/20 , G09G3/3266 , G09G3/36
CPC分类号： G09G3/2092 , G09G3/3233 , G09G3/3266 , G09G3/3677 , G09G3/3696 , G09G2300/0426 , G09G2300/0842 , G09G2310/0202 , G09G2310/0278 , G09G2310/0286 , G09G2310/0291 , G09G2320/0214 , G09G2320/0219 , G09G2320/0223 , G09G2320/0295
摘要： A scan driver includes a plurality of decoder type stages respectively outputting a plurality scan signals. An n-th stage includes a first input block configured to provide a first DC voltage to a first node in response to a plurality of selection signals, a pull-down block configured to pull down a first node voltage, a second input block configured to reduce a voltage drop of a second node voltage when a scan signal is output, and to provide a second DC voltage to a second node in response to the selection signals, a buffer block configured to output the first node voltage, that is a buffer output voltage, in response to the first node voltage and the second node voltage, and an output block configured to output the scan signal.
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