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公开(公告)号：US10942597B2
公开(公告)日：2021-03-09
申请号：US16503741
申请日：2019-07-05
发明人： Deog-Kyoon Jeong , Youngmin Park , Sangjin Pak , Jiheon Park , Jonghyun Oh , Sanghun Park
IPC分类号： G06F3/041
摘要： A display apparatus includes a display panel, a touch sensing unit, and a touch driving circuit. The touch sensing unit includes a transmission touch line. The touch driving circuit provides a touch driving signal to the transmission touch line. The touch driving circuit may include a switch group and a control switch group. The switch group may include a plurality of switch devices, each of which has one end connected to the transmission touch line. The control switch group may be connected to the other end of at least a portion of the switch devices, include a plurality of control switch devices and a capacitor device, and receive a driving voltage and a ground voltage. The touch driving signal has N voltage levels, where N is a natural number of 3 or more.
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公开(公告)号：US11784854B2
公开(公告)日：2023-10-10
申请号：US17401011
申请日：2021-08-12
发明人： Moon-Chul Choi , Sanghee Lee , Seungha Roh , Kwangho Lee , Deog-Kyoon Jeong
CPC分类号： H04L25/03019 , H04B1/16 , H04L7/02
摘要： A receiver includes an equalization circuit configured to output a data sample signal and an edge sample signal by sampling a data input signal according to clock signal, and to perform an equalization operation according to the data sample signal and the edge sample signal; and a clock gate circuit configured to select the clock signals from among a plurality of multi-phase clock signals according to a selection signal.
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公开(公告)号：US11636173B2
公开(公告)日：2023-04-25
申请号：US16831481
申请日：2020-03-26
发明人： Tae Jun Ham , Seonghak Kim , Sungjun Jung , Younghwan Oh , Jaewook Lee , Deog-Kyoon Jeong , Minsoo Lim
摘要： An accelerator includes a key matrix register configured to store a key matrix, a query vector register configured to store a query vector; and a preprocessor configured to calculate similarities between the query vector and the key matrix.
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公开(公告)号：US11011214B2
公开(公告)日：2021-05-18
申请号：US16582322
申请日：2019-09-25
发明人： Suhwan Kim , Deog-Kyoon Jeong , Sang-Yoon Lee , Joo-Hyung Chae , Chang-Ho Hyun
摘要： A data receiving circuit may include: a variable delay circuit suitable for generating a delayed strobe signal by delaying a strobe signal; a receiving circuit suitable for sampling data in synchronization with the delayed strobe signal; a phase shift circuit suitable for generating a shifted strobe signal by shifting a phase of the delayed strobe signal; a phase comparison circuit suitable for comparing phases of the data and the shifted strobe signal; and a delay adjusting circuit suitable for adjusting a delay value of the variable delay circuit in response to the phase comparison result of the phase comparison circuit.
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公开(公告)号：US10950279B2
公开(公告)日：2021-03-16
申请号：US16545805
申请日：2019-08-20
发明人： Deog-Kyoon Jeong , Jung Min Yoon , Hyungrok Do , Dae-Hyun Koh
摘要： A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.
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公开(公告)号：US10931305B2
公开(公告)日：2021-02-23
申请号：US16660653
申请日：2019-10-22
发明人： Hong Seok Choi , Jeongho Hwang , Hyungrok Do , Deog-Kyoon Jeong
摘要： A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.
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7.发明授权公开(公告)号：US10861546B2
公开(公告)日：2020-12-08
申请号：US16572275
申请日：2019-09-16
发明人： Hyunkyu Park , Suhwan Kim , Deog-Kyoon Jeong
摘要： A semiconductor memory device includes a memory cell array including a plurality of wordlines, a plurality of bitlines and a plurality of cells; a bitline decoder configured to couple a global bitline to one of the plurality of bitlines according to a bitline selection signal; a bitline driver configured to provide bitline current to the global bitline; a wordline decoder configured to couple a global wordline to one of the plurality of wordlines according to a wordline selection signal; a wordline driver configured to provide a wordline drive voltage to the global wordline during a write operation and to adjust the wordline drive voltage according to a write address; and a write control circuit configured to generate the wordline selection signal and the bitline selection signal, and to control the bitline decoder, the wordline decoder, and the bitline driver.
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公开(公告)号：US10361692B2
公开(公告)日：2019-07-23
申请号：US16149687
申请日：2018-10-02
发明人： Deog-Kyoon Jeong , Suhwan Kim , Joo-Hyung Chae
IPC分类号： H03K5/26 , H03K3/03 , G01R25/00 , H03H7/06 , H03K17/687
摘要： A duty cycle detector includes a first ring oscillator suitable for including an odd number of first inverters and generating a first periodic signal by using the first inverters, at least one inverter among the first inverters being enabled during a time interval when a clock has a first value, a second ring oscillator including an odd number of second inverters and suitable for generating a second periodic signal using the second inverters, at least one inverter among the second inverters being enabled during a time interval when the clock has a second value. The duty cycle detector further includes a frequency comparator suitable for comparing a frequency of the first periodic signal with a frequency of the second periodic signal and generating a duty cycle detection signal of the clock.
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公开(公告)号：US10284211B2
公开(公告)日：2019-05-07
申请号：US15494130
申请日：2017-04-21
发明人： Sungwoo Kim , Sungyong Cho , Hankyu Chi , Suhwan Kim , Deog-Kyoon Jeong
摘要： An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.
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公开(公告)号：US11757683B2
公开(公告)日：2023-09-12
申请号：US17698918
申请日：2022-03-18
发明人： Daeho Yun , Deog-Kyoon Jeong
CPC分类号： H04L25/03885 , H04L25/03057 , H04L27/01
摘要： A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.
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