Abstract:
There is provided a multilayer ceramic electronic component including a ceramic body including a plurality of dielectric layers stacked in a thickness direction and satisfying T/W>1.0 when it is defined that a width thereof is W and a thickness thereof is T, a plurality of first and second internal electrodes disposed in the ceramic body so as to face each other, having the dielectric layer interposed therebetween, and alternately exposed through both end surfaces of the ceramic body, and first and second external electrodes including head parts formed on both end surfaces of the ceramic body and two band parts connected to the head parts and formed on portions of upper and lower main surfaces of the ceramic body so as to be spaced apart from each other in a width direction, and electrically connected to the first and second internal electrodes, respectively.
Abstract:
There is provided a multi-layer ceramic electronic component including: a ceramic sintered body in which a plurality of dielectric layers are laminated; first and second internal electrodes formed in the ceramic sintered body; first and second external electrodes formed on both ends of the ceramic sintered body while covering a circumference thereof, and electrically connected to the first and second internal electrodes; and a sealing part including a glass component and formed in a gap between an outer surface of the ceramic sintered body and ends of the first and second external electrodes.
Abstract:
There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer; first and second internal electrodes disposed to face each other with the dielectric layer interposed therebetween within the ceramic body; and first and second external electrodes formed on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, wherein, when the dielectric layer is divided into three areas in a thickness direction of the ceramic body, an average size of dielectric grains in a middle area is different from that of dielectric grains in upper and lower areas, and when T1 denotes a thickness of the dielectric layer, T2 denotes a thickness of the middle area, and T3 and T4 denote thicknesses of the upper and lower areas adjacent to the first and second internal electrodes, T2≧0.45T1 and T3+T4≦0.55T1 are satisfied.