公开(公告)号：US20240063186A1

公开(公告)日：2024-02-22

申请号：US18301541

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： SEYONG LEE ,  Jungseok Ahn

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/73 ,  H01L24/16 ,  H01L2225/06513 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/05647 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05655 ,  H01L2224/0568 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05671 ,  H01L2224/05611 ,  H01L2224/05666 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/16145

Abstract: A semiconductor package includes a first semiconductor chip including a substrate having a first upper surface and a first lower surface opposite thereto. The substrate has a central region and corner regions surrounding the central region. A plurality of through electrodes passes through the central region. A bonding pad is electrically connected to the through electrode and has a first height. A plurality of dummy pads respectively extend from the first upper surface on the corner regions of the substrate and have a second height that is higher than the first height. A second semiconductor chip has a second upper surface and a second lower surface opposite thereto. The second semiconductor chip is disposed on the first semiconductor chip through conductive bumps disposed on the second lower surface and electrically connected to the bonding pads.