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公开(公告)号:US11768601B2
公开(公告)日:2023-09-26
申请号:US17343495
申请日:2021-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ramdas P. Kachare , Vijay Balakrishnan , Stephen G. Fischer , Fred Worley , Anahita Shayesteh , Zvi Guz
CPC classification number: G06F3/061 , G06F3/0656 , G06F3/0679 , G06F9/38 , G06F9/541 , G06F9/544
Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n−1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.
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2.
公开(公告)号:US20190243906A1
公开(公告)日:2019-08-08
申请号:US15934747
申请日:2018-03-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Timothy C. Bisson , Anahita Shayesteh , Changho Choi
CPC classification number: G06F16/13 , G06F3/064 , G06F3/0679 , G06F16/16 , G06F16/182
Abstract: A solid-state drive (SSD) includes: a plurality of data blocks; a plurality of flash channels and a plurality of ways to access the plurality of data blocks; and an SSD controller that configures a block size of the plurality of data blocks. A data file is stored in the SSD with one or more key-values pairs, and each key-value pair has a block identifier as a key and a block data as a value. A size of the data file is equal to the block size or a multiple of the block size.
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公开(公告)号:US20210294494A1
公开(公告)日:2021-09-23
申请号:US17343495
申请日:2021-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ramdas P. Kachare , Vijay Balakrishnan , Stephen G. Fischer , Fred Worley , Anahita Shayesteh , Zvi Guz
Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n−1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.
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4.
公开(公告)号:US10949341B2
公开(公告)日:2021-03-16
申请号:US16178569
申请日:2018-11-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Anahita Shayesteh , Jingpei Yang , Vijay Balakrishnan
IPC: G06F3/00 , G06F12/02 , G06F3/06 , G06F16/901
Abstract: According to one general aspect, an apparatus may include a storage memory to store a plurality of key-value pairs. The apparatus may include at least one snapshot counter configured to store an operation number associated with a respective snapshot of the plurality of key-value pairs. The apparatus may include a snapshot data structure configured to identify, for at least one key-value pair, which, if any, snapshot(s) the respective key-value pair is associated with.
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公开(公告)号:US20200183582A1
公开(公告)日:2020-06-11
申请号:US16269508
申请日:2019-02-06
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ramdas P. Kachare , Vijay Balakrishnan , Stephen G. Fischer , Fred Worley , Anahita Shayesteh , Zvi Guz
Abstract: A method includes: receiving, at an acceleration platform manager (APM) from an application service manager (ASM), application function processing information; allocating, by the APM, a first storage processing accelerator (SPA) from a plurality of SPAs, wherein at least one SPA of the plurality of SPAs comprises a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs comprising n SPEs, enabling the plurality of SPEs in the first SPA, wherein once enabled, the at least one SPE of the plurality of SPEs in the first SPA is configured to process data based on the application function processing information; determining, by the APM, if data processing is completed by the at least one SPE of the plurality of SPEs in the first SPA; and sending, by the APM, a result of the data processing by the SPEs of the first SPA, to the ASM.
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公开(公告)号:US11726930B2
公开(公告)日:2023-08-15
申请号:US17338654
申请日:2021-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ramdas P. Kachare , Zvi Guz , Son T. Pham , Anahita Shayesteh , Xuebin Yao , Oscar Prem Pinto
CPC classification number: G06F13/1668 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F9/547 , G06F13/4282 , G06F2213/0026
Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.
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公开(公告)号:US11030129B2
公开(公告)日:2021-06-08
申请号:US16794217
申请日:2020-02-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ramdas P. Kachare , Zvi Guz , Son T. Pham , Anahita Shayesteh , Xuebin Yao , Oscar Prem Pinto
Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.
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公开(公告)号:US10296264B2
公开(公告)日:2019-05-21
申请号:US15098111
申请日:2016-04-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sina Hassani , Anahita Shayesteh , Vijay Balakrishnan
Abstract: A method of selecting among a plurality of I/O streams through which data is to be written to a multi-streaming flash storage device is presented. According to an example embodiment, the method comprises: assigning write sequences of similar length to the same I/O streams; receiving instructions for a write operation, the instructions including a starting logical block address (LBA) and a number of blocks of data to be written; determining whether the write operation is part of an existing write sequence; identifying an I/O stream associated with an existing write sequence; and providing a stream ID of the identified I/O stream to the multi-streaming flash storage device.
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公开(公告)号:US12147358B2
公开(公告)日:2024-11-19
申请号:US18233870
申请日:2023-08-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Ramdas P. Kachare , Zvi Guz , Son T. Pham , Anahita Shayesteh , Xuebin Yao , Oscar Prem Pinto
Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.
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公开(公告)号:US20240020009A1
公开(公告)日:2024-01-18
申请号:US18370817
申请日:2023-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ramdas P. Kachare , Vijay Balakrishnan , Stephen G. Fischer , Fred Worley , Anahita Shayesteh , Zvi Guz
CPC classification number: G06F3/061 , G06F3/0656 , G06F9/38 , G06F9/544 , G06F9/541 , G06F3/0679
Abstract: A system includes a plurality of storage processing accelerators (SPAs), at least one SPA of the plurality of SPAs including a plurality of programmable processors or storage processing engines (SPEs), the plurality of SPEs including n SPEs (n is a natural number greater than zero), where 1st to (n−1) SPEs of the n SPEs are configured to provide an output of the SPE to a next SPE of the n SPEs in a pipeline to be used as an input of the next SPE; and an acceleration platform manager (APM) connected to the plurality of the SPAs and the plurality of SPEs, and configured to control data processing in the plurality of SPAs and the plurality of SPEs.
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