公开(公告)号：US20240212726A1

公开(公告)日：2024-06-27

申请号：US18544550

申请日：2023-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin SEO ,  Cheonan LEE ,  Sukkang SUNG

IPC: G11C7/10

CPC classification number: G11C7/1048

Abstract: A device includes an input/output circuit, wherein the input/output circuit includes: a control circuit configured to receive a signal indicating whether the device is activated; a variable voltage source configured to generate a variable voltage according to a control operation of the control circuit based on the signal received by the control circuit; an output driver including a first transistor and a second transistor; and a pad configured to output a current that is generated by the output driver, and wherein the variable voltage source is configured to provide the variable voltage to a body of the first transistor and a body of the second transistor.

公开(公告)号：US20240046994A1

公开(公告)日：2024-02-08

申请号：US18120244

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonan LEE ,  Kiwhan Song ,  Gyosoo Choo ,  Sukkang Sung

IPC: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.