公开(公告)号：US09741441B2

公开(公告)日：2017-08-22

申请号：US15232909

申请日：2016-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungryun Kim ,  Sangyong Yoon ,  Kiwhan Song

IPC: G11C16/06 ,  G11C16/28 ,  G11C16/34 ,  G11C16/10 ,  G11C7/22 ,  G11C11/56 ,  G11C16/04 ,  G11C16/32 ,  G06F3/06 ,  G11C16/30

CPC classification number: G11C16/28 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0679 ,  G11C7/227 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.

公开(公告)号：US20250105128A1

公开(公告)日：2025-03-27

申请号：US18745694

申请日：2024-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungjoon Yoo ,  Jungmin Seo ,  Kiwhan Song ,  Hanbyeol Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate having a plurality of substrate pads, a chip stack including a plurality of semiconductor chips each chip having a plurality of chip pads arranged along one edge of an upper surface and pad extensions extending from the plurality of chip pads to an adjacent side surface to the one edge. The semiconductor chips are stacked such that the adjacent side surfaces have a coplanar surface. A multichannel film having an insulating film and a plurality of conductive lines disposed connects the chip pads of the plurality of semiconductor chips to the plurality of substrate pads.

公开(公告)号：US09190163B2

公开(公告)日：2015-11-17

申请号：US14328913

申请日：2014-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hai-Seok Park ,  Boh-Chang Kim ,  Hyung Suk Kim ,  Kiwhan Song

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3427

Abstract: An operating method of a memory controller controlling a nonvolatile memory device including a plurality of pages includes receiving a read request and a logical address from an additional device; determining a program state of an upper unselected word line of a selected word line corresponding to the received logical address; and transmitting a physical address corresponding to the logical address, state information, and a read command to the nonvolatile memory device according to a result of the determination in response to the read request, wherein the state information indicates a level of a first unselect read voltage the nonvolatile memory device is to apply to the upper unselected word line.

Abstract translation: 控制包括多页的非易失性存储装置的存储器控​​制器的操作方法包括从附加装置接收读取请求和逻辑地址; 确定与所接收的逻辑地址相对应的所选字线的上未选字线的编程状态; 以及根据所述读取请求，根据所述确定的结果向所述非易失性存储器件发送对应于所述逻辑地址，状态信息和读取命令的物理地址，其中所述状态信息指示第一未选择读取电压的电平 非易失性存储器件应用于上部未选择的字线。

公开(公告)号：US09129696B2

公开(公告)日：2015-09-08

申请号：US14340773

申请日：2014-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun Joo ,  Kiwhan Song ,  Ju Seok Lee ,  Kihwan Choi

IPC: G11C16/08 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C2211/563

Abstract: A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells.

Abstract translation: 非易失性存储器件的软判决读取方法包括：接收软判决读命令，将读电压施加到所选择的字线，对分别连接到所选字线的选定存储单元的位线进行预充电，连续检测状态 的所选存储单元。 提供给所选字线的位线的预充电电压和读取电压在所选存储单元的感测状态期间不改变。

公开(公告)号：US12272409B2

公开(公告)日：2025-04-08

申请号：US18176347

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hong Kwon ,  Kiwhan Song ,  Gyosoo Choo

IPC: G11C7/22 ,  G11C16/04 ,  G11C16/20 ,  G11C16/26

Abstract: Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.

公开(公告)号：US20240029798A1

公开(公告)日：2024-01-25

申请号：US18176347

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hong KWON ,  Kiwhan Song ,  Gyosoo Choo

IPC: G11C16/26 ,  G11C16/20 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/20 ,  G11C16/0433

Abstract: Various example embodiments provide a flash memory device, comprising a cell string having a plurality of memory cells; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell from among the plurality of memory cells by precharging a sensing node connected to the bit line; and a voltage regulator providing a source voltage to the page buffer. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device according to the embodiment of the present invention may reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, according to the present invention, an OFF cell margin and an ON cell margin may be sufficiently secured by adjusting the level of the trip voltage Vtrip using the source voltage Vs.

公开(公告)号：US20250157543A1

公开(公告)日：2025-05-15

申请号：US18933556

申请日：2024-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbae Bang ,  Kiwhan Song

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffers respectively coupled to the plurality of memory cells through a plurality of bit line. Each page buffer of the plurality of page buffers includes a first transistor coupling a corresponding bit line of the plurality of bit lines to a first node, based on a first control signal, a second transistor coupling the first node to a sensing node, a sensing latch configured to sense data stored in a corresponding memory cell, based on a first voltage level of the sensing node, a forcing latch configured to store forcing data, a first discharge transistor including a first gate terminal configured to receive the forcing data, and a second discharge transistor including a second gate terminal configured to receive a discharge control signal.

公开(公告)号：US20250085340A1

公开(公告)日：2025-03-13

申请号：US18667974

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Takuya FAUTATSUYAMA ,  Wandong Kim ,  Kiwhan Song

IPC: G01R31/28 ,  H01L21/66

Abstract: A circuit for detecting defects includes a defect detection conductor provided in a peripheral region of a semiconductor die, an input pad connected to a first end of the defect detection conductor, an output pad connected to a second end of the defect detection conductor, a defect detection assembly connected to the defect detection conductor and configured to detect a defect of the defect detection conductor, and a controller configured to control operations of the defect detection assembly, where the defect detection assembly includes a reference voltage supply, a reference capacitor, a switching assembly, and a plurality of detection capacitors, and the switching assembly is configured to connect the reference capacitor to one of the reference voltage supply, a position adjacent to the input pad of the defect detection conductor, and a position adjacent to the output pad of the defect detection conductor.

公开(公告)号：US20240049471A1

公开(公告)日：2024-02-08

申请号：US18322040

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inho Kang ,  Seungyeon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Jaeeun Lee ,  Kiwhan Song

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B80/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B80/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A vertically-integrated nonvolatile memory device includes a peripheral circuit structure with a peripheral circuit therein, and cell array structure that is bonded to the peripheral circuit structure, and has a cell area and a connection area therein. The cell area includes a plurality of gate electrodes and a plurality of insulating layers alternately stacked, in the connection area. The plurality of gate electrodes include a cell stack having a staircase shape, a plurality of capacitor core contact structures configured to pass through the cell stack in the cell area, and a plurality of capacitor gate contact structures connected to the plurality of gate electrodes in the connection area. Each of the plurality of capacitor core contact structures includes: (i) a first core conductor electrically connected to the peripheral circuit, and (ii) a first cover insulating layer extending between the first core conductor and the plurality of gate electrodes, and constitutes a capacitor in which the first core conductor, the first cover insulating layer, and the plurality of gate electrodes are connected to the peripheral circuit.

公开(公告)号：US20240046994A1

公开(公告)日：2024-02-08

申请号：US18120244

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonan LEE ,  Kiwhan Song ,  Gyosoo Choo ,  Sukkang Sung

IPC: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.