SEMICONDUCTOR PACKAGE
    2.
    发明申请

    公开(公告)号:US20250105128A1

    公开(公告)日:2025-03-27

    申请号:US18745694

    申请日:2024-06-17

    Abstract: A semiconductor package includes a package substrate having a plurality of substrate pads, a chip stack including a plurality of semiconductor chips each chip having a plurality of chip pads arranged along one edge of an upper surface and pad extensions extending from the plurality of chip pads to an adjacent side surface to the one edge. The semiconductor chips are stacked such that the adjacent side surfaces have a coplanar surface. A multichannel film having an insulating film and a plurality of conductive lines disposed connects the chip pads of the plurality of semiconductor chips to the plurality of substrate pads.

    Operating method of nonvolatile memory device and operating method of memory controller controlling the nonvolatile memory device
    3.
    发明授权
    Operating method of nonvolatile memory device and operating method of memory controller controlling the nonvolatile memory device 有权
    非易失性存储器件的操作方法和控制非易失性存储器件的存储器控​​制器的操作方法

    公开(公告)号:US09190163B2

    公开(公告)日:2015-11-17

    申请号:US14328913

    申请日:2014-07-11

    CPC classification number: G11C16/26 G11C11/5642 G11C16/0483 G11C16/3427

    Abstract: An operating method of a memory controller controlling a nonvolatile memory device including a plurality of pages includes receiving a read request and a logical address from an additional device; determining a program state of an upper unselected word line of a selected word line corresponding to the received logical address; and transmitting a physical address corresponding to the logical address, state information, and a read command to the nonvolatile memory device according to a result of the determination in response to the read request, wherein the state information indicates a level of a first unselect read voltage the nonvolatile memory device is to apply to the upper unselected word line.

    Abstract translation: 控制包括多页的非易失性存储装置的存储器控​​制器的操作方法包括从附加装置接收读取请求和逻辑地址; 确定与所接收的逻辑地址相对应的所选字线的上未选字线的编程状态; 以及根据所述读取请求,根据所述确定的结果向所述非易失性存储器件发送对应于所述逻辑地址,状态信息和读取命令的物理地址,其中所述状态信息指示第一未选择读取电压的电平 非易失性存储器件应用于上部未选择的字线。

    Flash memory device for adjusting trip voltage using voltage regulator and sensing method thereof

    公开(公告)号:US12272409B2

    公开(公告)日:2025-04-08

    申请号:US18176347

    申请日:2023-02-28

    Abstract: Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.

    FLASH MEMORY DEVICE FOR ADJUSTING TRIP VOLTAGE USING VOLTAGE REGULATOR AND SENSING METHOD THEREOF

    公开(公告)号:US20240029798A1

    公开(公告)日:2024-01-25

    申请号:US18176347

    申请日:2023-02-28

    CPC classification number: G11C16/26 G11C16/20 G11C16/0433

    Abstract: Various example embodiments provide a flash memory device, comprising a cell string having a plurality of memory cells; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell from among the plurality of memory cells by precharging a sensing node connected to the bit line; and a voltage regulator providing a source voltage to the page buffer. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device according to the embodiment of the present invention may reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, according to the present invention, an OFF cell margin and an ON cell margin may be sufficiently secured by adjusting the level of the trip voltage Vtrip using the source voltage Vs.

    MEMORY DEVICE AND OPERATING METHOD OF THE SAME

    公开(公告)号:US20250157543A1

    公开(公告)日:2025-05-15

    申请号:US18933556

    申请日:2024-10-31

    Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffers respectively coupled to the plurality of memory cells through a plurality of bit line. Each page buffer of the plurality of page buffers includes a first transistor coupling a corresponding bit line of the plurality of bit lines to a first node, based on a first control signal, a second transistor coupling the first node to a sensing node, a sensing latch configured to sense data stored in a corresponding memory cell, based on a first voltage level of the sensing node, a forcing latch configured to store forcing data, a first discharge transistor including a first gate terminal configured to receive the forcing data, and a second discharge transistor including a second gate terminal configured to receive a discharge control signal.

    CIRCUIT FOR DETECTING DEFECTS
    8.
    发明申请

    公开(公告)号:US20250085340A1

    公开(公告)日:2025-03-13

    申请号:US18667974

    申请日:2024-05-17

    Abstract: A circuit for detecting defects includes a defect detection conductor provided in a peripheral region of a semiconductor die, an input pad connected to a first end of the defect detection conductor, an output pad connected to a second end of the defect detection conductor, a defect detection assembly connected to the defect detection conductor and configured to detect a defect of the defect detection conductor, and a controller configured to control operations of the defect detection assembly, where the defect detection assembly includes a reference voltage supply, a reference capacitor, a switching assembly, and a plurality of detection capacitors, and the switching assembly is configured to connect the reference capacitor to one of the reference voltage supply, a position adjacent to the input pad of the defect detection conductor, and a position adjacent to the output pad of the defect detection conductor.

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