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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10224331B2

    公开(公告)日：2019-03-05

    申请号：US15911922

    申请日：2018-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Raheel Azmat ,  Deepak Sharma ,  Su-Hyeon Kim ,  Chulhong Park

    IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L27/118 ,  H01L29/775

    Abstract: Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

    Semiconductor device and method of forming the same
    4.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US09490263B2

    公开(公告)日：2016-11-08

    申请号：US14312702

    申请日：2014-06-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sooyeon Jeon ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun ,  Yusun Lee ,  Hyun-Jong Lee

    IPC: H01L27/118 ,  H01L27/02

    CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11881

    Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

    Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线，并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。

    Semiconductor device and method of manufacturing the same
    7.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09418990B2

    公开(公告)日：2016-08-16

    申请号：US14736441

    申请日：2015-06-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Sharma Deepak ,  Chulhong Park

    IPC: H01L27/02 ,  H01L27/088

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

    Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

    Abstract translation: 半导体器件及其制造方法包括在与第一方向相交的第二方向上在第一方向上延伸并彼此间隔开的第一和第二栅极结构，设置在第一和第二栅极结构之间的虚拟栅极结构 在第一栅极结构和伪栅极结构之间的第一源极/漏极区域，在第二栅极结构和伪栅极结构之间的第二源极/漏极区域，设置在虚拟栅极结构上的连接接触点以及公共导线 提供在连接接点上。 虚拟栅极结构沿第一方向延伸。 连接触头沿第二方向延伸以将第一源极/漏极区域连接到第二源极/漏极区域。 所述公共导线被配置为通过所述连接接触到所述第一和第二源极/漏极区域的电压。

    Flip-flop layout architecture implementation for semiconductor device
    8.
    发明授权
    Flip-flop layout architecture implementation for semiconductor device 有权
    半导体器件的触发器布局架构实现

    公开(公告)号：US09324715B2

    公开(公告)日：2016-04-26

    申请号：US14504075

    申请日：2014-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel Azmat ,  Rwik Sengupta ,  Chulhong Park ,  Kwanyoung Chun

    IPC: H01L27/092 ,  H01L27/02 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207

    Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

    Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上，第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极，并且连接线设置在连接触头上以与连接触头交叉，并将第一栅电极连接到第四栅电极。

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230378155A1

    公开(公告)日：2023-11-23

    申请号：US18156494

    申请日：2023-01-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Panjae Park ,  Suhyeong Choi ,  Jiwook Kwon ,  Chulhong Park

    IPC: H01L27/02 ,  G06F30/392 ,  G06F30/394

    CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394

    Abstract: A semiconductor device includes first standard cells arranged in a first row on a substrate and respectively including a first base active region, second standard cells arranged in a second row adjacent to the first row and respectively including a second base active region, a power line extending in a first direction along a boundary between the first and second standard cells, and a device isolation layer on side surfaces of the first and second base active regions, wherein, in a plan view, the first standard cells and the second standard cells have a same cell height, the first base active region of each of the first standard cells includes a first active line having a first conductivity-type and a second active line having a second conductivity-type, the second base active region of each of the second standard cells includes a third active line having the first conductivity-type and a fourth active line having the second conductivity-type, the first active lines of the first standard cells arranged in the first row have a same first width, the third active lines of the second standard cells arranged in the second row have a same second width, and the first width is narrower than the second width.

    SEMICONDUCTOR DEVICES
    10.
    发明公开
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230378027A1

    公开(公告)日：2023-11-23

    申请号：US18113133

    申请日：2023-02-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Suhyeong CHOI ,  Jiwook Kwon ,  Byungju Kang ,  Chulhong Park ,  Kwanyoung Chun

    IPC: H01L23/48 ,  H01L23/522

    CPC classification number: H01L23/481 ,  H01L23/5226

    Abstract: A semiconductor device includes: a semiconductor substrate having power arrangement regions; a first interconnection structure disposed on the semiconductor substrate and including first interconnection patterns and power lines; a second interconnection structure disposed on the semiconductor substrate and including second interconnection patterns; and through-electrodes passing through each of the power arrangement regions and contacting the power lines, wherein the first interconnection patterns include first interconnection lines, wherein the power lines are disposed on a same height level as a first interconnection line, among the first interconnection lines, and are parallel to each other, wherein the power arrangement regions are parallel to each other, and wherein intersection regions, in which the power arrangement regions and the power lines intersect, include a plurality of first active intersection regions, one dummy intersection region, and a plurality of second active intersection regions, sequentially arranged.

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