公开(公告)号：US09390778B2

公开(公告)日：2016-07-12

申请号：US14798164

申请日：2015-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su-A Kim ,  Dae-Sun Kim ,  Dae-Jeong Kim ,  Sung-Min Ryu ,  Kwang-Il Park ,  Chul-Woo Park ,  Young-Soo Sohn ,  Jae-Youn Youn

IPC: G11C8/12 ,  G11C8/08 ,  G11C7/02 ,  G11C7/18 ,  G11C7/10

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 功率选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。

公开(公告)号：US09159398B2

公开(公告)日：2015-10-13

申请号：US14147545

申请日：2014-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Il Mok ,  Jong-Hyoung Lim ,  Dae-Sun Kim ,  Ji-Hyun Lee

IPC: G11C7/00 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4097 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4076 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages.

Abstract translation: 半导体器件可以包括连接到位线和第一字线的第一存储器单元，连接到互补位线和第二字线的第二存储器单元以及均衡器。 均衡器可以被配置为当位线和互补位线浮置时在第一时间段将位线和互补位线的电压从第一电压转换到不同于第一电压的第二电压， 并且当所述位线和互补位线浮置时，在所述第一时间段之后的第二时间周期将所述位线和所述互补位线中的至少一个的电压从所述第二电压转换到第三电压， 第三电压与第一和第二电压不同。