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公开(公告)号:US10825766B2
公开(公告)日:2020-11-03
申请号:US16285583
申请日:2019-02-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Ji Young Kim , Kyu Hee Han , Sung Bin Park , Yeong Gil Kim , Jong Min Baek , Kyoung Woo Lee , Deok Young Jung
IPC: H01L23/522 , H01L23/528 , H01L23/532 , H01L21/768 , H01L21/311
Abstract: A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.
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公开(公告)号:US20200227314A1
公开(公告)日:2020-07-16
申请号:US16545150
申请日:2019-08-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yeong Gil Kim , Han Seong Kim , Jong Min Baek , Ji Young Kim , Sung Bin Park , Deok Young Jung , Kyu Hee Han
IPC: H01L21/768 , H01L21/02 , H01L21/311
Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.
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公开(公告)号:US10510658B2
公开(公告)日:2019-12-17
申请号:US16039838
申请日:2018-07-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eui Bok Lee , Deok Young Jung , Sang Bom Kang , Doo-Hwan Park , Jong Min Baek , Sang Hoon Ahn , Hyeok Sang Oh , Woo Kyung You
IPC: H01L23/48 , H01L23/522 , H01L21/768 , H01L23/528
Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.
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公开(公告)号:US10804145B2
公开(公告)日:2020-10-13
申请号:US16545150
申请日:2019-08-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yeong Gil Kim , Han Seong Kim , Jong Min Baek , Ji Young Kim , Sung Bin Park , Deok Young Jung , Kyu Hee Han
IPC: H01L21/768 , H01L23/532 , H01L21/311 , H01L21/02 , H01L23/522
Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.
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公开(公告)号:US10096549B2
公开(公告)日:2018-10-09
申请号:US15480055
申请日:2017-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byung Hee Kim , Thomas Oszinda , Deok Young Jung , Jong Min Baek , Tae Jin Yim
IPC: H01L23/48 , H01L23/532 , H01L23/522 , H01L21/768
Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.
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公开(公告)号:US20180076140A1
公开(公告)日:2018-03-15
申请号:US15480055
申请日:2017-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byung Hee KIM , Thomas Oszinda , Deok Young Jung , Jong Min Baek , Tae Jin Yim
IPC: H01L23/532 , H01L23/522 , H01L21/768
CPC classification number: H01L23/5329 , H01L21/76802 , H01L21/76822 , H01L21/76829 , H01L21/76846 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/53238 , H01L23/53295
Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.
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