公开(公告)号：US20240395298A1

公开(公告)日：2024-11-28

申请号：US18794825

申请日：2024-08-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US12080379B2

公开(公告)日：2024-09-03

申请号：US17939016

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Baek Jin Lim ,  Youngchul Cho ,  Seungjin Park ,  Doobock Lee ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US20240046999A1

公开(公告)日：2024-02-08

申请号：US18148579

申请日：2022-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun Yoon ,  Seungjin Park ,  Doobock Lee ,  Seunghoon Lee ,  Baek Jin Lim ,  Youngdon Choi ,  Junghwan Choi

IPC: G11C16/32 ,  G11C16/04 ,  G06F1/10

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G06F1/10

Abstract: A nonvolatile memory device may include a variable sampler configured to process a data signal in an amplifier mode or a sampler mode in response to a control signal, a selection circuit configured to transmit the data signal output from the variable sampler to a flip-flop via a delay unit or to the flip-flop via a path that bypasses the delay unit in response to the control signal, a converter configured to amplify a data strobe signal, a clock distribution network configured to transmit the data strobe signal amplified by the converter to the variable sampler or delay the amplified data strobe signal for a predetermined time and transmit the amplified data strobe signal to the flip-flop in response to the control signal, and a path controller configured to generate the control signal according to an input/output mode.

公开(公告)号：US20240356553A1

公开(公告)日：2024-10-24

申请号：US18487448

申请日：2023-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu Lee ,  Seungjin Park ,  Doobock Lee ,  Youngchul Cho

IPC: H03K19/0185 ,  H03K3/356 ,  H03K17/22 ,  H03K19/003

CPC classification number: H03K19/018521 ,  H03K3/356113 ,  H03K17/223 ,  H03K19/00384

Abstract: A semiconductor device includes a first power node configured to supply a first power supply voltage, a pull-up circuit electrically connected between the first power node and an output node that is configured to output a signal, and a controller configured to output a pull-up control code to the pull-up circuit. The pull-up circuit includes a plurality of unit circuits electrically connected to each other in parallel between the first power node and the output node, and the plurality of unit circuits include a first unit circuit and a second unit circuit. The number of current paths provided by the first unit circuit between the first power node and the output node is different from the number of current paths provided by the second unit circuit between the first power node and the output node.