公开(公告)号：US20230180456A1

公开(公告)日：2023-06-08

申请号：US18059492

申请日：2022-11-29

申请人： Samsung Electronics Co., Ltd.

发明人： Euichul JEONG ,  Kiseok LEE ,  Wonki ROH ,  Hyungeun CHOI

IPC分类号： H10B12/00

CPC分类号： H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10885

摘要： A semiconductor memory device including a transistor body extending in a first horizontal direction and including a first source/drain region, a single-crystal channel layer, and a second source/drain region sequentially arranged in the first horizontal direction, a gate electrode layer extending in a second horizontal direction orthogonal to the first horizontal direction and covering upper and lower surfaces of the single-crystal channel layer, a bit line connected to the first source/drain region, extending in a vertical direction, and having a first width in the second horizontal direction, a spacer covering upper and lower surfaces of the first source/drain region and having a second width greater than the first width, and a cell capacitor on a side opposite to the bit line with respect to the transistor body in the first horizontal direction and including lower and upper electrode layers and a capacitor dielectric layer therebetween may be provided.

公开(公告)号：US20240130108A1

公开(公告)日：2024-04-18

申请号：US18369552

申请日：2023-09-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Euichul JEONG ,  Sang-Woon LEE ,  Sangho LEE ,  Moonyoung JEONG

IPC分类号： H10B12/00

CPC分类号： H10B12/315 ,  H10B12/05

摘要： A semiconductor memory device includes a substrate, a bit line on the substrate, word lines provided on the bit line and spaced apart in a first direction parallel to a top surface of the substrate, a back gate electrode provide between a pair of adjacent word lines among the word lines, active patterns provided between the back gate electrode and the pair of adjacent word lines, contact patterns respectively provided on the active patterns, a first back gate insulating pattern provided between the bit line and the back gate electrode, and a second back gate insulating pattern and a third back gate insulating pattern which are provided on the back gate electrode, where the back gate upper insulating pattern includes a material having a first dielectric constant and the back gate lower insulating pattern includes a material having a second dielectric constant that is greater than the first dielectric constant.

公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC分类号： H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC分类号： H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.