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公开(公告)号：US20210005629A1
公开(公告)日：2021-01-07
申请号：US17025479
申请日：2020-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L27/11582 , H01L27/11565 , H01L27/11556 , H01L27/11573 , H01L23/522 , G11C7/18 , H01L27/11519 , H01L27/11526 , G11C8/14
Abstract: A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.
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公开(公告)号：US20170062046A1
公开(公告)日：2017-03-02
申请号：US15351552
申请日：2016-11-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WON PARK , DONGKYO SHIM , KITAE PARK , SANG-WON SHIM
CPC classification number: G11C11/5642 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C29/021 , G11C29/028
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
Abstract translation: 非易失性存储器件包括：电压发生器，其向存储单元阵列的字线依次提供第一设定电压和第二设定电压;以及控制逻辑，包括时间控制单元，所述时间控制单元确定所述字线的字线建立时间 基于所述第一和第二设定电压之间的差，将所述第二设置电压提供给所述第二设置电压。
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公开(公告)号：US20230056261A1
公开(公告)日：2023-02-23
申请号：US17982255
申请日：2022-11-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L23/535 , H01L27/11573 , H01L27/11582
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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4.发明申请公开(公告)号：US20220020434A1
公开(公告)日：2022-01-20
申请号：US17489988
申请日：2021-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YONGHYUK CHOI , JAE-DUK YU , KANG-BIN LEE , SANG-WON SHIM , BONGSOON LIM
IPC: G11C16/10 , G11C16/08 , G11C16/34 , H01L25/065 , H01L25/18 , H01L23/00 , G11C16/04 , H01L27/11582 , H01L27/11556
Abstract: Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US20160343419A1
公开(公告)日：2016-11-24
申请号：US15225017
申请日：2016-08-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WON PARK , KITAE PARK , SANG-WON SHIM
CPC classification number: G11C8/08 , G11C5/02 , G11C7/04 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/30 , G11C16/32
Abstract: A word line driving method is for a nonvolatile memory device including a plurality of memory blocks having a plurality of strings which is formed in a direction perpendicular to a substrate and connected between bit lines and a common source line. The method includes applying an offset pulse to a word line for a predetermined time to shorten a word line setting time, and applying a target pulse having a level which is higher or lower than a level of the offset pulse to the word line after the predetermined time.
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Patent Agency Ranking
公开(公告)号：US20200168547A1
公开(公告)日：2020-05-28
申请号：US16592886
申请日：2019-10-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： BONGSOON LIM , SANG-WAN NAM , SANG-WON PARK , SANG-WON SHIM , HONGSOO JEON , YONGHYUK CHOI
IPC: H01L23/535 , H01L27/11582 , H01L27/11573
Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
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公开(公告)号：US20190325952A1
公开(公告)日：2019-10-24
申请号：US16503169
申请日：2019-07-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WON PARK , DONGKYO SHIM , KITAE PARK , SANG-WON SHIM
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
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公开(公告)号：US20180075918A1
公开(公告)日：2018-03-15
申请号：US15822320
申请日：2017-11-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TAE-HYUN KIM , BONG-SOON LIM , YOON-HEE CHOI , SANG-WON SHIM
CPC classification number: G11C16/3459 , G06F11/1068 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/52
Abstract: A memory device has a memory cell array with memory cells. A page buffer group generates page buffer signals according to a verify read result of the memory cells. A page buffer decoding unit generates a decoder output signal corresponding to the number of fail bits from the page buffer signals based on a first reference current. A slow bit counter outputs a count result corresponding to the number of fail bits from the decoder output signal based on a second reference current corresponding to M times the first reference current, where M is a positive integer. A pass/fail checking unit determines a program outcome with respect to the memory cells based on the count result and outputs a pass signal or a fail signal based on the determined program outcome.
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9.发明申请公开(公告)号：US20170278580A1
公开(公告)日：2017-09-28
申请号：US15425557
申请日：2017-02-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： BONGSOON LIM , SEOKMIN YOON , SANG-WON SHIM
CPC classification number: G11C16/3459 , G06F11/2094 , G11C7/106 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device may include a cell array, a first page buffer, and a second page buffer. The first page buffer may be connected to a first memory cell of the cell array and may store first sensing data generated by sensing whether a program operation of the first memory cell is completed during a program verify operation. The second page buffer may be connected to a second memory cell of the cell array. During the program verify operation, the second page buffer may generate and store first verify data based on second sensing data generated by sensing whether a program operation of the second memory cell is completed, may receive the first sensing data from the first page buffer, and may store second verify data generated by accumulating the first sensing data and the first verify data.
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公开(公告)号：US20150078095A1
公开(公告)日：2015-03-19
申请号：US14322335
申请日：2014-07-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANG-WON PARK , DONGKYO SHIM , KITAE PARK , SANG-WON SHIM
IPC: G11C16/26
CPC classification number: G11C11/5642 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3459 , G11C29/021 , G11C29/028
Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
Abstract translation: 非易失性存储器件包括：电压发生器，其向存储单元阵列的字线依次提供第一设定电压和第二设定电压;以及控制逻辑，包括时间控制单元，所述时间控制单元确定所述字线的字线建立时间 基于所述第一和第二设定电压之间的差，将所述第二设置电压提供给所述第二设置电压。
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