公开(公告)号：US20210125998A1

公开(公告)日：2021-04-29

申请号：US16990305

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOK-HYUN KIM ,  Joon Young KANG ,  YOUNGJUN KIM ,  JINHYUNG PARK ,  HO-JU SONG ,  SANG-JUN LEE ,  HYERAN LEE ,  BONG-SOO KIM ,  SUNGWOO KIM

IPC: H01L27/108

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

公开(公告)号：US20240015981A1

公开(公告)日：2024-01-11

申请号：US18132196

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEON IL LEE ,  SERYEUN YANG ,  HYERAN LEE

IPC: H10B51/30 ,  H10B51/20 ,  H10B51/40

CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B51/40

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a bit line that extends in a first direction; first and second word lines that extend in a second direction and cross the bit line; an active pattern on the bit line between the first and second word lines, the active pattern including first second vertical parts that are opposite to each other, and a horizontal part that extends between the first and second vertical parts; a first data storage pattern between the first word line and the first vertical part of the active pattern; a second data storage pattern between the second word line and the second vertical part of the active pattern; and a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line.

公开(公告)号：US20250159899A1

公开(公告)日：2025-05-15

申请号：US18944355

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYERAN LEE

IPC: H10B53/20 ,  H10B53/30

Abstract: A semiconductor memory device including a plurality of semiconductor patterns extending in a first horizontal direction on a substrate and having a first source/drain region, a channel region, and a second source/drain region, at least one interlayer separation insulating layer that separates the plurality of semiconductor patterns from each other in a vertical direction, a plurality of word lines each surrounding the channel region, a bit line connected to the first source/drain region and extending in the vertical direction, a plurality of first electrodes each on one side of the second source/drain region, a plurality of second electrodes each positioned inside respective ones of the plurality of first electrodes, a ferroelectric film positioned between the first electrode and the second electrode, a plate line that contacts the plurality of second electrodes, and a leaker configured to transfer charge between the first electrode and the second electrode.

公开(公告)号：US20230145857A1

公开(公告)日：2023-05-11

申请号：US17935119

申请日：2022-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYERAN LEE ,  Sohyun Park ,  Junhyeok Ahn

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063

Abstract: A semiconductor device includes a conductive contact plug disposed on a substrate, a bit line structure disposed on the conductive contact plug, first and second spacers, and a capping pattern disposed on the first and second spacers. The conductive contact plug includes a lower portion that has a first width and an upper portion that has a second width narrower than the first width. The bit line structure includes a conductive structure and an insulation structure stacked in a vertical direction. The first and second spacers are stacked on a sidewall of the lower portion of the conductive contact plug in a horizontal direction. The capping pattern covers a sidewall of the upper portion of the conductive contact plug. The first spacer directly contacts the sidewall of the lower portion of the conductive contact plug and includes air.