公开(公告)号：US20240023319A1

公开(公告)日：2024-01-18

申请号：US18326988

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/485 ,  H10B12/02

Abstract: A semiconductor device includes an active region defined by a device isolation layer, a pad layer on the device isolation layer and a first region of the active region, a first separation layer penetrating through the pad layer and extending in a first direction, a second separation layer penetrating through the pad layer and extending in a second direction, a word line below the second separation layer, extending in the second direction, and embedded in a substrate, a bit line extending in the first direction and connected to a second region of the active region, a contact structure on a side surface of the bit line and connected to the pad layer, and an data storage structure on the contact structure and connected to the contact structure. The first separation layer includes an airgap or a material having a dielectric constant less than a dielectric constant of silicon nitride.

公开(公告)号：US11980025B2

公开(公告)日：2024-05-07

申请号：US17705991

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok Ahn ,  Huijung Kim ,  Kiseok Lee ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/34 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes; an active region defined by an isolation film on a substrate, a word line in the substrate, the word line extending in a first direction and crossing the active region, a bit line above the word line and extending in a second direction, a contact between bit lines adjacent in the first direction, the contact connecting the active region and extending in a vertical direction, and a contact fence disposed on each of opposing side surfaces of the contact in the second direction and extending in the vertical direction, wherein the active region has a bar shape extending oblique to the first direction, and the contact fence includes a carbon-containing insulating film.

公开(公告)号：US20230387005A1

公开(公告)日：2023-11-30

申请号：US18201995

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn ,  Jinkuk Bae

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76832 ,  H01L21/76877 ,  H01L21/7682 ,  H01L23/53266

Abstract: A semiconductor device includes a first contact structure connected to the lower structure, a first conductive wiring connected to the first contact structure, a first etch-stop layer and an interlayer insulating layer sequentially provided on the first conductive wiring, a second contact structure passing through the first etch-stop layer, provided in the interlayer insulating layer, and connected to the first conductive wiring, a second conductive wiring provided on the second contact structure and provided in the interlayer insulating layer, a barrier layer including a first barrier portion on a bottom surface of the second contact structure, a second etch-stop layer provided on a top surface of the second conductive wiring and a top surface of the interlayer insulating layer, and an air gap between the barrier layer and the extension portion.

公开(公告)号：US20240315006A1

公开(公告)日：2024-09-19

申请号：US18424447

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Huijung Kim ,  Sangjae Park ,  Taejin Park ,  Junhyeok Ahn ,  Chansic Yoon ,  Myeongdong Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: A semiconductor device includes an active pattern array including active patterns on a substrate, a first contact structure on a central portion of each active pattern, a bit line structure on the first contact structure, a second contact structure on an end portion of each active pattern, a third contact structure on the second contact structure, a filling pattern between the bit line structure and the third contact structure and including a void, and a capacitor electrically connected to the third contact structure. The active pattern array includes active pattern rows spaced apart from each other in a first direction, and each active pattern row includes the active patterns spaced apart from each other in a second direction. Each active pattern extends in a third direction, and the active patterns in each active pattern row are aligned in the second direction.

公开(公告)号：US20240188284A1

公开(公告)日：2024-06-06

申请号：US18371663

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Kim ,  Chansic Yoon ,  Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/485

Abstract: A semiconductor device includes a gate electrode disposed within a cell region of a substrate, each of bit line structure pairs including a first bit line structure and a second bit line structure, and extension portion pairs disposed within an interface region of the substrate, each extension portion pair including a first extension portion and a second extension portion that are connected to the first bit line structure and the second bit line structure, respectively. The bit line structure pairs are spaced apart from each other by a first distance. In each bit line structure pair, the first bit line structure and the second bit line structure are spaced apart from each other by the first distance. In each extension portion pair, the first extension portion and the second extension portion are spaced apart from each other at a second distance less than the first distance.

公开(公告)号：US11770926B2

公开(公告)日：2023-09-26

申请号：US17530818

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok Ahn ,  Kiseok Lee ,  Huijung Kim

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

公开(公告)号：US20230155024A1

公开(公告)日：2023-05-18

申请号：US17969491

申请日：2022-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyeok Ahn ,  Sohyun Park

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L27/088 ,  H01L29/4236 ,  H01L27/108

Abstract: A semiconductor device includes a semiconductor substrate provided with active regions, an isolation layer defining each active region on the semiconductor substrate, gate electrodes overlapping the active regions and extending in a first direction parallel to an upper surface of the semiconductor substrate, an insulating barrier structure disposed at a level higher than a level of where the gate electrodes are disposed, the insulating barrier structure having a grid pattern including grid cells, bitlines extending in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate, and disposed at a level higher than a level of where the insulating barrier structure is disposed, and first contact plugs, each first contact plug being disposed in a corresponding grid cell of the grid cells of the insulating barrier structure.

公开(公告)号：US12289881B2

公开(公告)日：2025-04-29

申请号：US17948796

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Kim ,  Chansic Yoon ,  Hyosub Kim ,  Sohyun Park ,  Junhyeok Ahn

IPC: H10B12/00 ,  H10D64/23

Abstract: Provided is a semiconductor device including a conductive contact plug on a substrate, the conductive contact plug including a lower portion and an upper portion on the lower portion, the lower portion having a first width, and the upper portion having a second width less than the first width, a bit line structure on the conductive contact plug, the bit line structure including a conductive structure and an insulation structure provided in a vertical direction perpendicular to an upper surface of the substrate, and a first lower spacer, a second lower spacer, and a third lower spacer sequentially provided on a sidewall of the lower portion of the conductive contact plug in a horizontal direction parallel to the upper surface of the substrate, wherein an uppermost surface of the third lower spacer is higher than an upper surface of the first lower spacer and an upper surface of the second lower spacer.

公开(公告)号：US20230422488A1

公开(公告)日：2023-12-28

申请号：US18192329

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Sohyun Park ,  Chansic Yoon ,  Dongmin Choi ,  Seungbo Ko ,  Hyosub Kim ,  Jingkuk Bae ,  Woojin Jeong ,  Eunkyung Cha ,  Junhyeok Ahn

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/315

Abstract: A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.

公开(公告)号：US20230413538A1

公开(公告)日：2023-12-21

申请号：US18148566

申请日：2022-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeran Lee ,  Junhyeok Ahn ,  Kiseok Lee

IPC: H10B12/00 ,  H01L29/423 ,  H01L23/528

CPC classification number: H10B12/488 ,  H01L23/5283 ,  H10B12/482 ,  H01L29/4236

Abstract: An integrated circuit device includes a substrate comprising an active region and a word line trench, a word line extending longitudinally in a first horizontal direction in the word line trench, a buried insulating layer on the word line, a conductive plug on the substrate, and a pad structure on the substrate and having a portion in contact with a top surface of the active region and a portion in contact with the conductive plug. The pad structure includes a conductive pad having a bottom surface in contact with the top surface of the active region and a pad spacer in contact with a sidewall of the conductive pad and protruding beyond an inner sidewall of the word line trench in a second horizontal direction orthogonal to the first horizontal direction such that the pad spacer vertically overlaps a portion of the word line in the word line trench.