公开(公告)号：US20180331046A1

公开(公告)日：2018-11-15

申请号：US16026937

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Sooho SHIN ,  Juik LEE ,  Jun Ho LEE ,  Kwangmin KIM ,  Ilyoung MOON ,  Jemin PARK ,  Bumseok SEO ,  Chan-Sic YOON ,  Hoin LEE

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US20210408008A1

公开(公告)日：2021-12-30

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L27/24

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20240237331A1

公开(公告)日：2024-07-11

申请号：US18350427

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoin LEE ,  Byung-Hyun LEE ,  Hoouk LEE

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/315 ,  H01L29/42356 ,  H10B12/03 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including a cell array region and a core region disposed around the cell array region; a plurality of storage element contacts; a contact plug; and a contact plug spacer. The plurality of storage element contacts may include a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region, such that the first storage element contact is between the core region and the at least one second storage element contact. A step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.

公开(公告)号：US20190287977A1

公开(公告)日：2019-09-19

申请号：US16419947

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20240304691A1

公开(公告)日：2024-09-12

申请号：US18668743

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoin LEE ,  Kiseok LEE

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/423 ,  H01L29/402

Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

公开(公告)号：US20240280895A1

公开(公告)日：2024-08-22

申请号：US18381773

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam YEEM ,  Hoin LEE ,  Dongkyun LEE ,  Sangchul YANG ,  Byung-Hyun LEE

IPC: G03F1/70 ,  H01L21/027

CPC classification number: G03F1/70 ,  H01L21/027 ,  H10B12/315

Abstract: A method of fabricating a semiconductor device may include forming a target pattern on a first wafer by performing a first exposure process, measuring a misalignment value of the target pattern, calculating a block misalignment value and a pattern misalignment value based on the misalignment value, calculating a block correction value based on the block misalignment value and calculating a pattern correction value based on the pattern misalignment value, and performing a second exposure process on a second wafer, based on the block correction value and the pattern correction value.

公开(公告)号：US20230035660A1

公开(公告)日：2023-02-02

申请号：US17683765

申请日：2022-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoin LEE ,  Kiseok LEE

IPC: H01L29/423 ,  H01L29/40

Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.