公开(公告)号：US20240268101A1

公开(公告)日：2024-08-08

申请号：US18471900

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SangJae PARK ,  Seung-Bo KO ,  Keunnam KIM ,  Jongmin KIM ,  Hui-Jung KIM ,  Taejin PARK ,  Chan-Sic YOON ,  Kiseok LEE ,  Myeong-Dong LEE ,  Hongjun LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and being adjacent to each other in a second direction, the first and second active patterns, each of which includes first and second edges spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge of the first active pattern, a second storage node pad and a second storage node contact sequentially provided on the second edge of the second active pattern, and a fence pattern between the first and the second storage node contacts. Bottom and top surfaces of the first storage node contact are located at first and second levels, respectively. In a third direction, a width of the fence pattern at the first level is less than a width of the fence pattern at the second level.

公开(公告)号：US20230262961A1

公开(公告)日：2023-08-17

申请号：US17957242

申请日：2022-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic YOON ,  Kiseok LEE

IPC: H01L27/108

CPC classification number: H01L27/10823 ,  H01L27/10876

Abstract: A semiconductor device includes a substrate having an active region and a gate structure crossing the active region. The gate structure may include a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate, a metal-containing pattern on the gate pattern, and a barrier pattern interposed between the gate pattern and the metal-containing pattern and extended to face opposite side surfaces of the metal-containing pattern.

公开(公告)号：US20180331046A1

公开(公告)日：2018-11-15

申请号：US16026937

申请日：2018-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Sooho SHIN ,  Juik LEE ,  Jun Ho LEE ,  Kwangmin KIM ,  Ilyoung MOON ,  Jemin PARK ,  Bumseok SEO ,  Chan-Sic YOON ,  Hoin LEE

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes an alignment key on a substrate. The alignment key includes a first sub-alignment key pattern with a first conductive pattern, a second conductive pattern, and a capping dielectric pattern that are sequentially stacked on the substrate, an alignment key trench that penetrates at least a portion of the first sub-alignment key pattern, and a lower conductive pattern in the alignment key trench. The alignment key trench includes an upper trench that is provided in the capping dielectric pattern that has a first width, and a lower trench that extends downward from the upper trench and that has a second width less than the first width. The lower conductive pattern includes sidewall conductive patterns that are separately disposed on opposite sidewalls of the lower trench.

公开(公告)号：US20240306377A1

公开(公告)日：2024-09-12

申请号：US18488229

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin KIM ,  Kiseok LEE ,  Seung-Bo KO ,  Chan-Sic YOON ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/01 ,  H10B12/315

Abstract: A semiconductor device including a first active pattern and a second active pattern each extending along a first direction and arranged along a second direction intersecting the first direction each of the first and second active patterns including a central part, a first edge part, and a second edge part, a storage node pad on the first edge part of the first active pattern, and a bit-line node contact on the central part of the first active pattern, wherein a top surface of the bit-line node contact is located at a higher level than a top surface of the storage node pad may be provided.

公开(公告)号：US20230422486A1

公开(公告)日：2023-12-28

申请号：US18109442

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Jongmin KIM ,  Hyo-Sub KIM ,  Hui-Jung KIM ,  Sohyun PARK ,  Junhyeok AHN ,  Chan-Sic YOON ,  Myeong-Dong LEE ,  Woojin JEONG ,  Wooyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/34 ,  H10B12/053 ,  H10B12/485

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

公开(公告)号：US20190287977A1

公开(公告)日：2019-09-19

申请号：US16419947

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20230354588A1

公开(公告)日：2023-11-02

申请号：US18117604

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Junhyeok AHN ,  Keunnam KIM ,  Chan-Sic YOON ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/02

Abstract: A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

公开(公告)号：US20210125980A1

公开(公告)日：2021-04-29

申请号：US17132699

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20190326278A1

公开(公告)日：2019-10-24

申请号：US16288590

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Dongoh KIM ,  Myeong-Dong LEE

IPC: H01L27/06 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.