公开(公告)号：US20180120918A1

公开(公告)日：2018-05-03

申请号：US15711397

申请日：2017-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ohsung KWON ,  Youngjun YOO ,  Hojun SHIM ,  Kwanggu LEE

IPC: G06F1/32

Abstract: A method of controlling a link state of a communication port of a storage device according to the present inventive concepts includes setting the link state of the communication port to a link active state that can exchange data with a host, determining a holding time of a first standby state among link states of the communication port, changing the link state of the communication port to the first standby state, monitoring whether an exit event occurs during the holding time from the time when a transition to the first standby state occurs, and in response to an exit event not occurring during the holding time, changing the link state of the communication port to a second standby state. A recovery time from the first standby state to the link active state is shorter than a recovery time from the second standby state to the link active state.

公开(公告)号：US20140149706A1

公开(公告)日：2014-05-29

申请号：US14088837

申请日：2013-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun SHIM ,  Eunchan KIM

IPC: G06F12/02

CPC classification number: G06F12/1081 ,  G06F12/0238 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/214 ,  G06F2212/7203

Abstract: A data transferring method of a storage device is provided. The method may include transferring a first data to a first outbound area, transferring the first data sent to the first outbound area to a first area of a main memory corresponding to a first address programmed by an address translation unit, transferring a second data to a second outbound area in response to an indication that the address translation unit is to be reprogrammed, and transferring the second data sent to the second outbound area to the first outbound area.

Abstract translation: 提供了一种存储装置的数据传送方法。 该方法可以包括将第一数据传送到第一出站区域，将发送到第一出站区域的第一数据传送到与由地址转换单元编程的第一地址相对应的主存储器的第一区域，将第二数据传送到 响应于要对地址转换单元重新编程的指示的第二出站区域，以及将发送到第二出站区域的第二数据传送到第一出站区域。

公开(公告)号：US20140149692A1

公开(公告)日：2014-05-29

申请号：US14090042

申请日：2013-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunchan KIM ,  Hojun SHIM

IPC: G06F3/06

CPC classification number: G06F13/385

Abstract: A memory controller and an operating method of a memory controller are provided. The operating method includes receiving a command issue from the external host; fetching a command corresponding to the command issue from a memory of the external host in response to the command issue; and controlling the external memory to perform the fetched command. The command is fetched immediately after the command issue is received independently from an execution of a previously fetched command. The memory controller includes a first interface which communicates with a host; and a second interface which communicates with the first interface and with an external memory and is recognized as storage by the host. The memory controller performs the operating method,

Abstract translation: 提供存储器控制器和存储器控制器的操作方法。 操作方法包括从外部主机接收命令问题; 响应于命令问题，从外部主机的存储器获取与命令问题相对应的命令; 并控制外部存储器执行取出的命令。 在执行命令发出后立即取出该命令，独立于先前提取的命令的执行。 存储器控制器包括与主机进行通信的第一接口; 以及与第一接口和外部存储器通信并被主机识别为存储的第二接口。 存储器控制器执行操作方法，

公开(公告)号：US20210028956A1

公开(公告)日：2021-01-28

申请号：US16816992

申请日：2020-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boeok SEO ,  Seonbong KIM ,  Hojun SHIM

IPC: H04L12/40 ,  H04L29/08 ,  H04L12/24 ,  H04L12/725

Abstract: A method of controlling a master device includes, providing a measured service level by measuring a service level with respect to requests of a master device that is connected to a slave device through an interconnect device and generates the request to demand services from the slave device and controlling a power level of a request control circuit included in the master device based on the measured service level. Power consumption of the master device and the system including the master device is reduced without performance degradation by controlling the power level of the request control circuit adaptively based on the measured service level.

公开(公告)号：US20140156880A1

公开(公告)日：2014-06-05

申请号：US14095177

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun SHIM

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/1668

Abstract: A memory controller is provided which includes a host interface configured to provide an interface for communication with a host; a buffer memory configured to store user data and metadata of the user data; and a DMA controller configured to access the buffer memory to check the metadata and to provide user data corresponding to a logical block address requested from a host to the host interface according to the checking result. The metadata includes status information of the user data stored at the buffer memory. Before providing the host interface with user data corresponding to a first logical block address requested from the host, the DMA controller checks metadata of user data corresponding to a second logical block address requested from the host.

Abstract translation: 提供了一种存储器控制器，其包括被配置为提供用于与主机通信的接口的主机接口; 缓冲存储器，被配置为存储用户数据和用户数据的元数据; 以及DMA控制器，被配置为访问缓冲存储器以检查元数据，并根据检查结果向与主机接口请求的逻辑块地址相对应的用户数据提供。 元数据包括存储在缓冲存储器中的用户数据的状态信息。 在向主机接口提供对应于从主机请求的第一逻辑块地址的用户数据之前，DMA控制器检查对应于从主机请求的第二逻辑块地址的用户数据的元数据。

公开(公告)号：US20140149608A1

公开(公告)日：2014-05-29

申请号：US14088909

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun SHIM ,  Eunchan KIM

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A memory controller is provided. The memory controller may comprise a first interface configured to provide an interface for communications with a host, and a second interface configured to communicate with the host through the first interface and to provide an interface for communications with a memory. The second interface may include an emulation engine configured to generate a Direct Memory Access (DMA) setup Frame Information Structure (FIS) including ready state information for data communications with the host in response to a command transferred from the host. The second interface may include a storage engine configured to access the host to fetch a physical region descriptor (PRD) before the DMA setup FIS is received from the emulation engine.

Abstract translation: 提供存储器控制器。 存储器控制器可以包括被配置为提供用于与主机通信的接口的第一接口和被配置为通过第一接口与主机通信并且提供用于与存储器通信的接口的第二接口。 第二接口可以包括被配置为响应于从主机传送的命令而生成包括用于与主机进行数据通信的就绪状态信息的直接存储器访问（DMA）建立帧信息结构（FIS）的仿真引擎。 第二接口可以包括被配置为在从仿真引擎接收到DMA建立FIS之前访问主机以获取物理区域描述符（PRD）的存储引擎。

公开(公告)号：US20240296131A1

公开(公告)日：2024-09-05

申请号：US18662097

申请日：2024-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmuk HWANG ,  Jaegeun PARK ,  Hojun SHIM ,  Byungchul YOO

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1642 ,  G06F13/161 ,  G06F13/1689 ,  G06F13/28

Abstract: A storage controller includes a command manager and a direct memory access (DMA) engine. The command manager receives a first submission queue doorbell from an external device, fetches a first command including a first latency from the external device in response to the first submission queue doorbell, and determines a first timing to write a first completion into the external device based on the first latency, the first completion indicating that the first command is completely processed. The DMA engine receives a request signal requesting processing of the first command from the command manager, transfer data, which the first command requests, based on a DMA transfer in response to the request signal, and outputs a complete signal, which indicates that the first command is completely processed, to the command manager.

公开(公告)号：US20200250121A1

公开(公告)日：2020-08-06

申请号：US16853373

申请日：2020-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun SHIM

IPC: G06F13/40 ,  G06F3/06

Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.

公开(公告)号：US20140149767A1

公开(公告)日：2014-05-29

申请号：US14088602

申请日：2013-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunchan KIM ,  Bumseok YU ,  Hojun SHIM

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3253 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D50/20

Abstract: A memory controller and an operating method of a memory controller are provided. The operating method includes detecting that a bus of an external host connected with the memory controller enters a first power saving mode; entering a second power saving mode of the memory controller according to a result of the detecting; detecting a wake-up process of the bus of the external host; and waking up the memory controller while the bus of the external host executes the wake-up process. The waking up of the memory controller is ended before the wake-up process of the bus of the external host is completed.

Abstract translation: 提供存储器控制器和存储器控制器的操作方法。 操作方法包括检测与存储器控制器连接的外部主机的总线进入第一省电模式; 根据检测结果进入存储器控制器的第二省电模式; 检测外部主机的总线的唤醒过程; 并在外部主机的总线执行唤醒过程时唤醒内存控制器。 内存控制器的唤醒在外部主机的总线的唤醒过程完成之前结束。