公开(公告)号：US20140246725A1

公开(公告)日：2014-09-04

申请号：US14196512

申请日：2014-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseob Lee ,  Hyuckjoon Kwon

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  G11C11/4097 ,  H01L27/0207

Abstract: An integrated circuit memory device includes a substrate having a sense amplifier region or a word line driver region comprising circuits configured to operate a memory cell array. The substrate further includes a conjunction region adjacent the sense amplifier region or word line driver region and defining a boundary therebetween. A plurality of gate patterns extends on the substrate. The gate patterns include peripheral gate patterns extending in the sense amplifier region or word line driver region, and conjunction gate patterns extending in the conjunction region. Ones of the conjunction gate patterns and ones of the peripheral gate patterns proximate the boundary extend substantially parallel along the boundary between the conjunction region and the sense amplifier region or word line driver region.

Abstract translation: 集成电路存储器件包括具有读出放大器区域或字线驱动器区域的衬底，该区域包括被配置为操作存储器单元阵列的电路。 衬底还包括与感测放大器区域或字线驱动器区域相邻并在其间限定边界的连接区域。 多个栅极图案在基板上延伸。 栅极图案包括在读出放大器区域或字线驱动器区域中延伸的外围栅极图案，以及在连接区域中延伸的连接栅极图案。 连接栅极图案和靠近边界的外围栅极图案的一个沿着连接区域和读出放大器区域或字线驱动器区域之间的边界基本上平行延伸。

公开(公告)号：US20240346222A1

公开(公告)日：2024-10-17

申请号：US18510969

申请日：2023-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Han ,  Jong-Seong Kim ,  Sungju Jang ,  Hyuckjoon Kwon ,  Sunghoon Kim ,  Raehyun Song

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Disclosed is an operating method of an electronic device that includes a processor and supports manufacture of a semiconductor device. The operating method includes receiving, at the processor, circuit schematics for the manufacture of the semiconductor device, partitioning, at the processor, circuit components of the circuit schematics into at least two mats, calculating, at the processor, availability of placement and routing of the circuit components, based on limited connecting elements electrically connected to the circuit components, for each of the at least two mats, and performing, at the processor, the placement and routing to generate a layout image for the manufacture of the semiconductor device when the availability indicates that the placement and routing is available. The limited connecting elements include vertical lines, which electrically connect an upper portion and a lower portion of the semiconductor device, at limited locations of the semiconductor device.

公开(公告)号：US20250031377A1

公开(公告)日：2025-01-23

申请号：US18602749

申请日：2024-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon Kim ,  Chang-Bum Kim ,  Hyuckjoon Kwon

IPC: H10B43/40 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B80/00

Abstract: A three-dimensional (3D) semiconductor memory device is provided. The device includes: a memory cell region; and a peripheral circuit configured to control the memory cell region. The memory cell region includes: a cell array region including memory cells arranged vertically along a vertical direction; and a connection region including ends of word lines that are connected to the memory cells, wherein the ends form a stair-step configuration. The peripheral circuit includes a peripheral circuit region overlapping the connection region along the vertical direction. The peripheral circuit region includes a first main pass transistor electrically connected to a first word line of the word lines, and a first dummy pass transistor electrically separated from the word lines. The first main pass transistor and the first dummy pass transistor are arranged along a first direction perpendicular to the vertical direction.

公开(公告)号：US20250069961A1

公开(公告)日：2025-02-27

申请号：US18800813

申请日：2024-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyong Choi ,  Sooyeol Yang ,  Jaeeun Lee ,  Hyuckjoon Kwon ,  Jinwon Choi ,  Takuya Futatsuyama

IPC: H01L21/66 ,  G01R31/28

Abstract: A semiconductor multi-layer structure includes a first semiconductor wafer including a plurality of first pads, a second semiconductor wafer including a plurality of second pads combined with the plurality of first pads, and a test circuit configured to apply a first voltage to a reference combination portion in which a preset first reference pad among the plurality of first pads is combined with a preset second reference pad among the plurality of second pads and apply a second voltage to a comparison combination portion in which at least one first pad among the plurality of first pads is combined with at least one second pad among the plurality of second pads, wherein the test circuit compares a voltage distributed based on a resistance ratio of the reference combination portion to the comparison combination portion with a preset reference voltage to determine whether the at least one first pad is aligned with the at least one second pad.

公开(公告)号：US20190189186A1

公开(公告)日：2019-06-20

申请号：US16034604

申请日：2018-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bok-Yeon Won ,  Hyuckjoon Kwon

IPC: G11C11/408 ,  H01L27/02 ,  H01L27/108

CPC classification number: G11C11/4085 ,  H01L27/0207 ,  H01L27/10805

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a first keeper transistor that is connected to a first word line. The semiconductor memory device includes a second keeper transistor that is connected to a second word line. The first keeper transistor and the second keeper transistor have a merged channel. In some embodiments, the first keeper transistor and the second keeper transistor are in a sub-word line driver.