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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250159868A1

    公开(公告)日：2025-05-15

    申请号：US18783044

    申请日：2024-07-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Selyung Yoon ,  Daehyeon Kwon ,  Donggeon Kim ,  Bok-Yeon Won

    IPC: H10B12/00 ,  H01L23/522

    Abstract: A semiconductor device includes a substrate, a transistor on the substrate, a bit line structure electrically connected to the transistor, a channel layer on the bit line structure, a gate structure intersecting the bit line structure, a first conductive line electrically connecting the transistor and the bit line structure, an upper shield line overlapping the first conductive line, and side shield lines spaced apart from each other with the first conductive line interposed therebetween. The upper shield line and the side shield lines are electrically separated from the first conductive line and the bit line structure.

    Sense amplifier having offset cancellation
    4.
    发明授权
    Sense amplifier having offset cancellation 有权

    公开(公告)号：US10803925B2

    公开(公告)日：2020-10-13

    申请号：US16829044

    申请日：2020-03-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-Wook Kim ,  Hyuk-Joon Kwon ,  Sang-Keun Han ,  Bok-Yeon Won

    IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/02 ,  G11C5/06 ,  G11C11/4096 ,  G11C11/408

    Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

    SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONS
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES HAVING ADJUSTABLE I/O SIGNAL LINE LOADING THAT SUPPORTS REDUCED POWER CONSUMPTION DURING READ AND WRITE OPERATIONS 审中-公开

    公开(公告)号：US20240105255A1

    公开(公告)日：2024-03-28

    申请号：US18322894

    申请日：2023-05-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Jun Lee ,  Sang-Yun Kim ,  Jonghyuk Kim ,  Bok-Yeon Won

    IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

    CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

    Abstract: A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n-1th connection control transistor is configured to electrically short the n-1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.

    Magnetic memory devices
    6.
    发明授权
    Magnetic memory devices 有权

    公开(公告)号：US11127789B2

    公开(公告)日：2021-09-21

    申请号：US16887541

    申请日：2020-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Han-Na Cho ,  Bok-Yeon Won ,  Oik Kwon

    IPC: H01L27/22 ,  H01L43/02 ,  H01L23/528 ,  H01L23/522 ,  H01L43/10

    Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

    Sense amplifier having offset cancellation
    7.
    发明授权
    Sense amplifier having offset cancellation 有权

    公开(公告)号：US11043257B2

    公开(公告)日：2021-06-22

    申请号：US16989207

    申请日：2020-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-Wook Kim ,  Hyuk-Joon Kwon ,  Sang-Keun Han ,  Bok-Yeon Won

    IPC: G11C11/4091 ,  G11C5/02 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/06 ,  G11C7/06

    Abstract: A sense amplifier includes a sense amplifying unit, first and second isolation units, and first and second offset cancellation unit. The sense amplifying unit includes a first P-type metal-oxide-semiconductor (PMOS) transistor, a second PMOS transistor, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a second NMOS transistor. In a layout of the sense amplifier, the first and second PMOS transistors are disposed in a central region of the sense amplifier, the first and second NMOS transistors are disposed at opposite sides of the sense amplifier from each other, the first isolation unit and the first offset cancellation unit are disposed between the first PMOS transistor and the first NMOS transistor, and the second isolation unit and the second offset cancellation unit are disposed between the second PMOS transistor and the second NMOS transistor. In other layouts, the locations of the PMOS transistors and NMOS transistors may be reversed.

    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
    10.
    发明申请
    SUB-WORD-LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME 有权

    公开(公告)号：US20220406360A1

    公开(公告)日：2022-12-22

    申请号：US17685849

    申请日：2022-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokjae Lee ,  Bok-Yeon Won ,  Kyoungmin Kim ,  Donggeon Kim ,  Myeongsik Ryu ,  Sangwook Park ,  Inseok Baek

    IPC: G11C11/408 ,  H01L27/108

    Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

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