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公开(公告)号：US20220115046A1
公开(公告)日：2022-04-14
申请号：US17346853
申请日：2021-06-14
发明人： Hyunsuk Kang , Jungjune Park , Kyoungtae Kang , Junha Lee , Byunghoon Jeong
摘要： A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.
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公开(公告)号：US20240347080A1
公开(公告)日：2024-10-17
申请号：US18406726
申请日：2024-01-08
发明人： Hyunsuk Kang , Jeongsu Lee , Eunji An , Jungjune Park , Chiweon Yoon
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A semiconductor device includes a first pull-up circuit connected between a first power node supplying a first power voltage and an output node through which a signal is output, and including a plurality of NMOS transistors; a second pull-up circuit connected in parallel to the first pull-up circuit between the first power node and the output node and including a plurality of PMOS transistors; and a control circuit outputting a first pull-up code to the first pull-up circuit and outputting the second pull-up code to the second pull-up circuit. In a first operating mode, the signal swings between a first low level lower than the first power voltage, and a first high level lower than ½ times the first power voltage, resistance of the first pull-up circuit is determined based on the first pull-up code, and resistance of the second pull-up circuit is determined based on the second pull-up code.
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公开(公告)号：US11869860B2
公开(公告)日：2024-01-09
申请号：US17479194
申请日：2021-09-20
发明人： Hyunsuk Kang , Daehoon Na , Chiweon Yoon
IPC分类号： G11C7/10 , H01L23/00 , H01L25/065 , H01L25/18 , G11C5/02
CPC分类号： H01L24/08 , H01L25/0657 , H01L25/18 , G11C5/025 , H01L2224/08145 , H01L2225/06506 , H01L2225/06562
摘要： A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.
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公开(公告)号：US11581025B2
公开(公告)日：2023-02-14
申请号：US17346853
申请日：2021-06-14
发明人： Hyunsuk Kang , Jungjune Park , Kyoungtae Kang , Junha Lee , Byunghoon Jeong
摘要： A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.
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公开(公告)号：US20220236917A1
公开(公告)日：2022-07-28
申请号：US17479194
申请日：2021-09-20
发明人： Hyunsuk Kang , Daehoon Na , Chiweon Yoon
IPC分类号： G06F3/06 , H01L25/065 , H01L25/18 , H01L23/00
摘要： A storage device includes a controller including first and second pins and configured to output a multi-level chip enable signal through the second pin, and a memory device. The memory device includes third and fourth pins respectively connected to the first and second pins, and a plurality of memory chips commonly connected to the fourth pin. The plurality of memory chips respectively include a plurality of resistors connected to one another in a daisy-chain structure between the third pin and a first voltage terminal. The plurality of memory chips are configured to respectively generate a plurality of reference voltage periods that divide between a voltage level of the third pin and a voltage level of the first voltage terminal based on the plurality of resistors.
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